RT9643 datasheet(3/17 Pages) RICHTEK

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RT9643

DS9643-03 August 2007

www.richtek.com

Table 1. While S5àS0àS3

State

S3#I

EN(S5#) VCC_EN 5VSB_DRV

VDDQ

VTT_OUT 1.2 OUT

3V Dual 5V Dual

OFF

+5VSB

OFF

+5VMAIN

Start up Sequencing

The VCC pin provides power to all logic and analog control functions of the regulator including : After VCC is above

UVLO, the start-up sequence begins as shown in Figure 1.

Figure 1

T0 to T3 :

After initial power-up, the IC will ignore all logic inputs for a time period (T3-T0) of about :

The 3V Dual LDO is in regulation. The 3.3V LDO’ s slew rate is limited by the discharge slope of CSS. If 3V MAIN has

come up prior to this time, the 3V DUAL node will already be pre-charged through the body diode of Q5 (see Figure 1).

T3 to T4 :

The IC waits about 100

μs before initiating soft-start on VDDQ to allow CSS time to fully discharged. The IC is

in “SLEEP” or S5 state when EN is low. In S5 only the 3.3V LDO is on. If the IC is in S5 at T4, CSS will be held to 0V.

T4 to T5 :

While First time to enter S0, The IC will start VDDQ only if 5V_MAIN is above its UVLO threshold (5V_MAIN

o.k.) and S3#I is high.

T5 to T7 :

After VDDQ is stabilized (when CSS is above about 1.5V) which will allow the 1.2V LDO and the VTT LDO to

soft start. To ensure that the VDDQ output is not subjected to large transient currents during transition, the VTT and 1.2V

LDO slew rates are limited by the slew rate of the CSS until the LDO is in regulation. In addition, the VTT regulator is

current limited.

T8 (S0 to S3) :

Dropping the S3#I signal. When this occurs, VCC_EN goes low, and the 3.3V LDO turns on. The 1.2V

LDO and the VTT LDO are turned off, and CSS is discharged to 2V. 5VSB_DRV pulls low to turn on the P-Channel 5V

DUAL switch.

6.5

UVLO

~4V

1.5V

2.0V

2.5V

T4 T5 T6 T7

5VSB

VDDQ

3V Dual

VTT_OUT/

1.2 OUT

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