IR3087PBF

SYSTEM THEORY OF OPERATION

XPhase

The XPhase

requiring small size, design flexibility, low voltage, high current and fast transient response. The architecture can

control converters of any phase number where flexibility facilitates the design trade-off of multiphase converters.

The scalable architecture can be applied to other applications which require high current or multiple output voltages.

As shown in Figure 1, the XPhase

each using a single Phase IC. The Control IC communicates with the Phase ICs through a 5-wire analog bus, i.e.

bias voltage, phase timing, average current, error amplifier output, and VID voltage. The Control IC incorporates all

the system functions, i.e. VID, PWM ramp oscillator, error amplifier, bias voltage, and fault protections etc. The

Phase IC implements the functions required by the converter of each phase, i.e. the gate drivers, PWM comparator

and latch, over-voltage protection, and current sensing and sharing.

There is no unused or redundant silicon with the XPhase

controller that can be configured for 2, 3, or 4 phase operation. PCB Layout is easier since the 5 wire bus

eliminates the need for point-to-point wiring between the Control IC and each Phase. The critical gate drive and

current sense connections are short and local to the Phase ICs. This improves the PCB layout by lowering the

parasitic inductance of the gate drive circuits and reducing the noise of the current sense signal.

0.1uF

CCS

RCS

CCS

0.1uF

CIN

RCS

VOUT+

VOUT-

VOUT SENSE-

VID0

VID3

12V

VOUT SENSE+

VID4

VID2

VR HOT

POWER GOOD

VID5

VID1

ENABLE

OC

INPUT/OUTPUT

ADDITIONAL PHASES

<< CURRENT SENSE

>> PWM CONTROL

>> PHASE TIMING

>> BIAS VOLTAGE

IR3081A

CONTROL

IC

>> VID VOLTAGE

CURRENT SHARE

CURRENT SHARE

COUT

CONTROL BUS

IR3087

PHASE IC

BIAS VOLTAGE

GATE VOLTAGE

REGULATOR

IR3087

PHASE IC

PHASE HOT

PHASE HOT

PHASE FAULT

VID VOLTAGE

PWM CONTROL

PHASE TIMING

BIAS VOLTAGE

VID VOLTAGE

PWM CONTROL

PHASE TIMING

OC OC

OC OC OC

OC OC OC

Figure 1. System Block Diagram

Page 7 of 35