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TCP862-DOC Datasheet(PDF) 1 Page - TEWS Technologies GmbH |
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TCP862-DOC Datasheet(HTML) 1 Page - TEWS Technologies GmbH |
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1 / 2 page ![]() TEWS TECHNOLOGIES GmbH keeps the right to change technical specification without further notice. All trademarks mentioned are property of their respective owners. 10/2009 TEWS TECHNOLOGIES GmbH Am Bahnhof 7 25469 Halstenbek, Germany Phone: +49 (0) 4101 4058 0 Fax: +49 (0) 4101 4058 19 e-mail: info@tews.com www.tews.com The Embedded I/O Company TCP862 4 Channel High Speed Synch/Asynch Serial Interface Application Information The TCP862 is a standard 3U 32 bit CompactPCI module with four high speed serial data communication channels. The TCP862-10 provides front panel I/O via HD68 SCSI-3 type connector and TCP862-20 additionally provides rear I/O via J2. An Infineon PEF 20534 DMA Supported Serial Communication Controller (DSCC4) with integrated bus master PCI interface is used. Several interrupt sources can generate interrupts on INTA for each channel. Interrupts can be enabled and disabled separately. A 14.7456 MHz oscillator provides standard asynchronous baud rates. An additional 24 MHz oscillator is provided for other baud rates. A 10 MHz oscillator is used for the maximum synchronous baud rate of 10 Mbit/s. Each channel can support many serial communication protocols such as HDLC, SDLC, PPP, asynchronous, monosynchronous, bisynchronous. Multiprotocol transceivers are used for the line interface. The physical interface can be selected by software individually for each channel as EIA-232, EIA-422, EIA- 449, EIA-530, EIA-530A, V.35, V.36 or X.21. The TCP862 supports Receive Data (RxD +/-), Transmit Data (TxD +/-), Receive Clock (RxC +/-), Transmit Clock (TxC +/-), Ready-To-Send (RTS +/-), Clear-To-Send (CTS +/-), Carrier-Detect (CD +/-) and GND for each channel. Additionally serial channel three provides Data- Set-Ready (DSR3 +/-) and Data-Terminal-Ready (DTR3 +/-), both over front I/O only. The local control logic provides additional features, e.g. multiplexing and inverting clock signals and supporting all clock modes of the DSCC4 conveniently. The device contains a central receive and transmit FIFO of 128 long words (32 bit) each. Furthermore each channel has a 17 long words deep receive FIFO and an 8 long words deep transmit FIFO. For First Time Users the Engineering Documentation TCP862-ED is recommended. The Engineering Documentation includes TCP862-DOC, schematics and data sheets. Driver support (TDRV001-SW-xx) for different operating systems is available. Technical Information Standard 3U 32 Bit CompactPCI module conforming to PICMG 2.0 R3.0 PCI 2.1 compliant master/slave interface Board size: 160 mm x 100 mm Four high speed synchronous/asynchronous serial interfaces based on Infineon PEF20534 Support of RxD, TxD, RxC, TxC, RTS, CTS, CD and GND on HD68 front connector, parallel to rear connector J2 (TCP862-20); DTR3 and DSR3 only at front I/O Physical interface (individually programmable per channel): EIA-232, EIA-422, EIA-449, EIA-530, EIA- 530A, V.35, V.36 and X.21 Maximum data rate: 10 Mbit/s (synchronous), 2 Mbit/s (asynchronous), internal or external provided clock EIA-232: up to 115.2 kbit/s Operating temperature range: -40°C to +85°C |
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