ADS1174IPAPR datasheet(24/35 Pages) TI

24 / 35 page

www.ti.com

POWER-UP SEQUENCE

DRDY

(SPI)

DOUT

(Frame-Sync)

InternalReset

CLK

1VNom

(1)

IOVDD

1VNom

(1)

DVDD

3.5VNom

(1)

AVDD

ValidData

CLK

128

DATA

NOTE:(1)Thepower-supplyresetthresholdsareapproximate.

ADS1174

ADS1178

SBAS373 – OCTOBER 2007

Figure 24 shows the power-up sequence of the

ADS1174/78. The power supplies can be sequenced

The ADS1174/78 has three power supplies: AVDD,

in any order. Each supply has an internal reset circuit

DVDD, and IOVDD. AVDD is the analog supply that

where the outputs are summed together to generate

powers the modulator, DVDD is the digital supply that

an internal global power-on reset. After the supplies

powers the digital core, and IOVDD is the digital I/O

have exceeded the reset thresholds, 218 fCLK cycles

power supply. The IOVDD and DVDD power supplies

are

counted

before

the

converter

initiates

the

can be tied together if desired. To achieve rated

conversion process. After all the fCLK cycles are

performance, it is critical that the power supplies are

counted, the data for 128 conversions is suppressed

bypassed with 0.1

μF and +10μF capacitors placed as

by the ADS1174/78 to allow output of fully-settled

close as possible to the supply pins. A single 1

μF

data. In SPI protocol, DRDY is held high during this

ceramic capacitor may be substituted in place of the

interval. In frame-sync protocol, DOUT is forced to

two capacitors.

zero. The power supplies should be applied before

any analog or digital pin is driven.

Figure 24. Power-Up Sequence

Submit Documentation Feedback

Product Folder Link(s): ADS1174 ADS1178

ADS1174IPAPR Datasheet(PDF) 24 Page - Texas Instruments

ADS1174IPAPR Datasheet(HTML) 24 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35

Datasheet Download

Link URL