74ALVC374 datasheet(8/17 Pages) NXP

8 / 17 page

74ALVC374_2

Product data sheet

Rev. 02 — 17 October 2007

8 of 17

NXP Semiconductors

74ALVC374

Octal D-type ﬂip-ﬂop; positive-edge trigger; 3-state

[1]

Typical values are measured at Tamb =25 °C

[2]

tpd is the same as tPHL and tPLH.

ten is the same as tPZH and tPZL.

tdis is the same as tPHZ and tPLZ.

[3]

CPD is used to determine the dynamic power dissipation (PD in µW).

PD =CPD × VCC2 × fi × N+ Σ(CL × VCC2 × fo) where:

fi = input frequency in MHz; fo = output frequency in MHz

CL = output load capacitance in pF

VCC = supply voltage in Volts

N = number of inputs switching

Σ(C

L × VCC

× f

o) = sum of the outputs

tsu

set-up time

Dn to CP; see Figure 9

VCC = 1.65 V to 1.95 V

0.8

−0.1

VCC = 2.3 V to 2.7 V

0.8

0.1

VCC = 2.7 V

0.8

0.3

VCC = 3.0 V to 3.6 V

0.8

0.0

hold time

Dn to CP; see Figure 9

VCC = 1.65 V to 1.95 V

0.8

−0.1

VCC = 2.3 V to 2.7 V

0.8

0.1

VCC = 2.7 V

0.8

0.4

VCC = 3.0 V to 3.6 V

0.7

−0.1

fmax

maximum frequency

see Figure 7

VCC = 2.3 V to 2.7 V

100

200

MHz

VCC = 2.7 V

100

200

MHz

VCC = 3.0 V to 3.6 V

150

300

MHz

CPD

power dissipation

capacitance

per ﬂip-ﬂop; VI = GND to VCC;VCC = 3.3 V

[3]

outputs HIGH or LOW state

outputs 3-state

Table 7.

Dynamic characteristics …continued

Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 10.

Symbol

Parameter

Conditions

−40 °C to +85 °C

Unit

Min

Typ[1]

Max

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