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TMPR4937 Datasheet(PDF) 378 Page - Toshiba Semiconductor |
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TMPR4937 Datasheet(HTML) 378 Page - Toshiba Semiconductor |
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378 / 552 page  Chapter 11 Serial I/O Port 11-18 Bit Mnemonic Field Name Description Read/Write 7 RDIS Reception Data Full Receive DMA/Interrupt Status (Default: 0) This bit is set when valid data of the amount set by the Receive FIFO Request Trigger Level (RDIL) of the FIFO Control register (SIFCR) is stored in the Receive FIFO. R/W0C 6 STIS Status Change Status Change Interrupt Status (Default: 0) This bit is set when at least one of the interrupt statuses selected by the Status Change Interrupt Condition field (STIE) of the DMA/Interrupt Control Register (SIDICR) becomes “1”. R/W0C 5 Reserved ⎯ 4:0 RFDN Reception Data Stage Status Receive FIFO Data Number (Default: 00000) This field indicates how many stages of reception data remain in the Receive FIFO (0 – 16 stages). R Figure 11.4.3 DMA/Interrupt Status Register (2/2) |
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