TMPR4937 datasheet(56/552 Pages) TOSHIBA

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Chapter 3 Signals

3-2

3.1.2

SDRAM Interface Signals

Table 3.1.2 SDRAM Interface Signals

Signal Name

Type

Description

Initial State

SDCLK[3:0]

Output

SDRAM Controller Clock

Clock signals used by SDRAM. The clock frequency is the same as the G-Bus clock

(GBUSCLK) frequency.

When these clock signals are not used, the pins can be set to H using the SDCLK

Enable field of the configuration register (CCFG.SDCLKEN[3:0]).

All High

SDCLKIN

Input/output SDRAM Feedback Clock input

Feedback clock signal for SDRAM controller input signals.

Setting the SDCLKINEN bit of the pin configuration register causes the TX4937 to

feed back signals internally, making SDCLKIN an output signal.

Input

CKE

Output

Clock Enable

CKE signal for SDRAM.

High

SDCS[3:0]*

Output

Synchronous Memory Device Chip Select

Chip select signals for SDRAM.

All High

RAS*

Output

Row Address Strobe

RAS signal for SDRAM.

High

CAS*

Output

Column Address Strobe

CAS signal for SDRAM.

High

WE*

Output

Write Enable

WR signal for SDRAM.

High

DQM[7:0]

Output

Data Mask

During a write cycle, the DQM signals function as a data mask. During a read cycle,

they control the SDRAM output buffers. The bits correspond to the following data bus

signals:

DQM[7]:DATA[63:54], DQM[6]:DATA[53:48]

DQM[5]:DATA[47:40], DQM[4]:DATA[39:32]

DQM[3]:DATA[31:24], DQM[2]:DATA[23:16]

DQM[1]:DATA[15:8], DQM[0]:DATA[7:0]

Connect any one of the DQM[3:0] to SDRAM which connects CB.

All High

CB[7:0]

Input/output

ECC/Parity Check Bit

ECC/parity check bit signals. The bits correspond to the following data bus signals:

CB[7]:DATA[63:54],

CB[6]:DATA[53:48]

CB[5]:DATA[47:40],

CB[4]:DATA[39:32]

CB[3]:DATA[31:24],

CB[2]:DATA[23:16]

CB[1]:DATA[15:8],

CB[0]:DATA[7:0]

CB[7:0] share pins with other function signals (refer to Section “3.3 Pin multiplex”).

Input

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