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TMPR4937 Datasheet(PDF) 50 Page - Toshiba Semiconductor |
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TMPR4937 Datasheet(HTML) 50 Page - Toshiba Semiconductor |
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50 / 552 page ![]() Chapter 1 Overview and Features 1-4 (5) Serial I/O port (SIO) The TX4937 has an on-chip 2-channel asynchronous serial I/O interface (full duplex UART) • Full duplex UART × 2 channels • On-chip baud rate generator • FIFO Transmission: on-chip 8-bit × 8-stage FIFO Reception: on-chip 13-bit × 16-stage (data: 8 bits; status: 5 bits) FIFO • Supports DMA transfer (6) Timer/Counter control (TMR) The TX4937 has an on-chip 3-channel timer/counter • 32-bit setup counter × 3 channels • Supports 3 modes: Interval Timer mode, Pulse Generator mode, Watchdog Timer mode • Timer output pins: 2 pins • Count clock input pin: 1 pin • Watchdog external reset pin: 1 pin (7) Parallel I/O port (PIO) The TX4937 has a 16-bit parallel I/O port (8 bits of which are shared with CB[7:0]) • Can set I/O direction and port type (totem pole output/open drain output) during output for each bit (8) AC-link Controller (ACLC) The TX4937 on-chip AC-link Controller can connect and manipulate audio and/or modem CODECs described in “Audio CODEC ’97 Revision 2.1”. • Supports up to 2 CODECs • Supports 16-bit PCM stereo channel recording and playback • Supports 16-bit surround, center, LFE channel playback • Supports variable rate audio recording and playback • Supports Line 1 for modem CODEC and GPIO slot • Supports AC-link low-power mode, Wake Up, and Warm Reset Supports sample data input/output by DMA transfer (9) Interrupt Controller (IRC) The Interrupt Controller built into the TX4937 receives interrupt requests and external interrupts from the TX4937 on-chip peripheral circuits and issues interrupt requests to the TX49/H3 core. This controller has a 16-bit flag register that generates interrupt requests to an external device or the TX49/H3 core. • Supports 19 types of internal interrupts from the on-chip peripheral circuits and 6 external interrupt signal inputs • Sets 8 priority levels for each interrupt input |
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