TMPR4937 datasheet(171/552 Pages) TOSHIBA

171 / 552 page

Chapter 8 DMA Controller

8-15

When the Destination Burst Inhibit bit (DMCCRn.DBINH) is set, data written from the FIFO to

the Destination Address is divided into multiple 8-byte Single Write transfers, then transfer is

executed.

When the Burst Inhibit bit is set, the TX4937 always performs an 8-byte Single transfer. For

accesses to an external I/O device, a Single transfer is divided into multiple accesses, depending

on its bus width. Thus, the address changes during a Single transfer. For more on this, see Section

7.3.5, "Data Bus Size." To continually access a fixed address in an external I/O device, program

the trasnfer size (DMCCRn.XFSZ) to the bus width of the I/O device and perform Single transfers

with the Burst Inhibit bit cleared.

8.3.8.3

Double Word Byte Swapping

When the Reverse Byte bit (REVBYTE) of the DMA Channel Configuration Register

(DMCCRn) is set, read double word data is written after byte swapping is performed. For

example, if the read data is “0x01234567_90ABCDEF”, then the data “0xEFCDAB89_67452301”

is written.

The Reverse Byte bit can only be set when the REVBYTE column of Table 8.3.3 is set so “0/1”

is indicated.

TMPR4937 Datasheet(PDF) 171 Page - Toshiba Semiconductor