TMPR4937 datasheet(194/552 Pages) TOSHIBA

194 / 552 page

Chapter 8 DMA Controller

8-38

8.4.9

DMA Count Register (DM0CNTRn, DM1CNTRn)

Offset Address: DMAC0 0xB018 (ch. 0) / 0xB058 (ch. 1) / 0xB098 (ch. 2) / 0xB0D8 (ch. 3)

DMAC1 0xB818 (ch. 0) / 0xB858 (ch. 1) / 0xB898 (ch. 2) / 0xB8D8 (ch. 3)

Reserved

: Type

: Initial value

Reserved

: Type

: Initial value

Reserved

DMCNTR[25:0]

R/W

: Type

⎯

: Initial value

DMCNTR[15:0]

R/W

: Type

⎯

: Initial value

Bit

Mnemonic

Field Name

Description

Read/Write

63:26

Reserved

⎯

25:0

DMCNTR

Count

Count Register (Default: undefined)

This register sets the byte count that is transferred by the DMA Channel

only by the size of the data transferred during a single bus operation.

Refer to “8.3.7.1 Channel Register Settings During Single Address

Transfer” and “8.3.8.1 Channel Register Settings During Dual Address

Transfer” for more information.

R/W

Figure 8.4.9 DMA Count Register

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