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TMPR4937 Datasheet(PDF) 231 Page - Toshiba Semiconductor

Part # TMPR4937
Description  64-Bit TX System RISC TX49 Family
PDF  552 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMPR4937 Datasheet(HTML) 231 Page - Toshiba Semiconductor

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Chapter 9 SDRAM Controller
9-15
9.3.10.3 Adding Read Latency for Each ECC/Parity Mode
When using the ECC/parity function, memory access latency is added according to which
ECC/parity mode is selected, whether errors will be generated or not, the error type to be
generated, and whether or not to generate bus errors. Table 9.3.6 shows in cycles the memory
Read access latency that will be added based on NOP mode operation under each condition.
Table 9.3.6 Read Latency Added for Each ECC/Parity Mode
ECC/Parity Mode
Bus Error
Notification
(ECCCR.MEB)
Error Type/Operation
Added Read Latency
(in cycles)
NOP Mode
⎯
⎯
0
No error
0
Disable
SBErr: Do not correct
MBErr: Correct
0
No error
1
EC Mode
Enable
SBErr: Do not correct
MBErr: Do not correct
2
No error
1
Disable
SBErr: Correct
MBErr: Do not correct
2
No error
1
ECC Mode
Enable
SBErr: Correct
MBErr: Do not correct
2
No error
1
SBErr: Correct & scrub
Max. 22
Disable
MBErr: Do not correct
3
No error
1
SBErr: Correct & scrub
Max. 22
ECC + scrub Mode
Enable
MBErr: Do not correct
2
No error
0
Disable
MBErr: Do not correct
0
No error
1
Even Parity Mode
Odd Parity Mode
Enable
MBErr: Do not correct
1
SBErr
= Single-bit error
MBErr
= Multi-bit error



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