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TMPR4937 Datasheet(PDF) 272 Page - Toshiba Semiconductor |
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TMPR4937 Datasheet(HTML) 272 Page - Toshiba Semiconductor |
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272 / 552 page ![]() Chapter 10 PCI Controller 10-14 PCI Reset is detected by either using the PCI Bus Reset Signal as the TX4937 overall reset signal or using the PCI Bus Reset Signal assertion detection device that the system provides. Then, the software reset the PCI Controller. The software uses a hardware reset (PCICCFG.HRST) of the PCI Controller Configuration Register to reset the PCI Controller. 10.3.9 Power Management The TX4937 PCI Controller supports power management functions that are compliant to PCI Bus Power Management Interface Specifications Version 1.1. The PCI Host device controls the system status by reporting the power management state to the PCI Satellite device. Also, the PCI Satellite device uses the PME* signal to report requests for changing the power management state or to report to the PCI Host device that a power management event has occurred. 10.3.9.1 Power Management State In the case of the PCI Bus Power Management Interface Specifications, four power management states are defined from State D0 to State D3. The TX4937 supports states D0 through D3. Figure 10.3.7 illustrates the power management state transition. After Power On Reset, or when transitioning from the D3HOT state to the D0 state, the power management state becomes uninitialized D0. If initialized by the system software at this point, the state transitions to D0 Active. If an external PCI Host device writes 11b (D3HOT) to the PowerState field of the Power Management Control Status Register (PMCSR) of the Configuration space when in the Satellite mode, then the Power Management State Change bit (P2GSTATUS.PMSC) of the P2G Status Register is set and transitions to the D3HOT state. It then becomes possible to report Power State Change interrupts. The PowerState field value can be read from the PowerState field (PCISSTATUS.PS) of the Satellite Mode PCI Status Register. The TX4937 uses the software to change the system status after a status change is detected. Figure 10.3.7 Transition of the Power Management States D0 Uninitialized D0 Active D3hot D3cold PCI RST** (RESET**) VCCCut-off Software Reset Power On Reset (RESET**) Initialization by the System Software Change PMCSR PowerState |
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