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TMP88CS34FG Datasheet(PDF) 7 Page - Toshiba Semiconductor |
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TMP88CS34FG Datasheet(HTML) 7 Page - Toshiba Semiconductor |
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7 / 215 page  TMP88CS34/CP34 2007-09-12 88CS34-7 Operational Description 1. CPU Core Functions The CPU core consists of a CPU, a system clock controller, and an interrupt controller. This section provides a description of the CPU core, the program memory, the data memory, the external memory interface, and the reset circuit. 1.1 Memory Address Map The TMP88CS34/CP34 memory consists of four blocks: ROM, RAM, SFR (Special Function Register), and DBR (Data Buffer Register). They are all mapped to a 1-Mbyte address space. Figure 1.1.1 shows the TMP88CS34/CP34 memory address map. There are 16 banks of the general-purpose register. The register banks are also assigned to the RAM address space. Figure 1.1.1 Memory Address Map ROM: Read Only Memory includes Program memory, Character data memory for OSD RAM: Random Access Memory includes Data memory, Stack, General-purpose register banks SFR: Special Function Register includes I/O ports, Peripheral hardware control registers, Peripheral hardware status registers System control registers, Interrupt control registers, Program status word DBR: Data Buffer Register includes Control register for on-screen display (OSD) Remote-control-receive control/status registers, ROM correction control registers Test video signal control registers 128 bytes 64 bytes 1536 bytes 128 bytes 64 bytes 128 bytes 64 bytes 128 bytes 65280 bytes 64 bytes TMP88CS34 00000H 0003FH 00040H 000BFH 000C0H 006BFH 00F80H 00FFFH 04000H 13EFFH FFF00H FFF3FH FFF40H FFF7FH FFF80H FFFFFH RAM SFR DBR ROM 128 bytes 128 bytes 1536 bytes 48896 bytes 64 bytes 64 bytes TMP88CP34 006BFH 00F80H 00FFFH 04000H 0FEFFH 00000H 0003FH 00040H 000BFH 000C0H FFF00H FFF3FH FFF40H FFF7FH FFF80H FFFFFH |
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