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ST10F273E Datasheet(PDF) 38 Page - STMicroelectronics |
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ST10F273E Datasheet(HTML) 38 Page - STMicroelectronics |
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38 / 179 page  Internal Flash memory ST10F273E 38/179 5.5.5 Flash non volatile access protection register 1 low FNVAPR1L (0x0E DFBC) NVR Delivery value: FFFFh 5.5.6 Flash non volatile access protection register 1 high FNVAPR1H (0x0E DFBE) NVR Delivery value: FFFFh 5.5.7 Access protection The I-Flash module has one level of access protection (access to data both in Reading and Writing): if bit ACCP of FNVAPR0 is programmed at 0, the I-Flash module becomes access protected: data in the I-Flash module can be read only if the current execution is from the I- Flash module itself. Protection can be permanently disabled by programming bit PDS0 of FNVAPR1H, in order to analyze rejects. Protection can be permanently enabled again by programming bit PEN0 of FNVAPR1L. The action to disable and enable again Access Protections in a permanent way can be executed a maximum of 16 times. Trying to write into the access protected Flash from internal RAM or external memories will be unsuccessful. Trying to read into the access protected Flash from internal RAM or external memories will output a dummy data (software trap 0x009Bh). When the Flash module is protected in access, also the data access through PEC of a peripheral is forbidden. To read/write data in PEC mode from/to a protected bank, first it is necessary to temporarily unprotect the Flash module. In the following table a summary of all levels of possible Access protection is reported: in particular, supposing to enable all possible access protections, when fetching from a 15 14 13 12 11 10 987 6543 210 PDS15 PDS14 PDS13 PDS12 PDS11 PDS10 PDS9 PDS8 PDS7 PDS6 PDS5 PDS4 PDS3 PDS2 PDS1 PDS0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Table 22. Flash non volatile access protection register 1 low Bit Function PDS(15:0) Protections disable 15-0 If bit PDSx is programmed at 0 and bit PENx is erased at 1, the action of bit ACCP is disabled. Bit PDS0 can be programmed at 0 only if both bits DBGP and ACCP have already been programmed at 0. Bit PDSx can be programmed at 0 only if bit PENx-1 has already been programmed at 0. 15 14 13 12 11 10 987 654 321 0 PEN15 PEN14 PEN13 PEN12 PEN11 PEN10 PEN9 PEN8 PEN7 PEN6 PEN5 PEN4 PEN3 PEN2 PEN1 PEN0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Table 23. Flash non volatile access protection register 1 high Bit Function PEN15-0 Protections enable 15-0 If bit PENx is programmed at 0 and bit PDSx+1 is erased at 1, the action of bit ACCP is enabled again. Bit PENx can be programmed at 0 only if bit PDSx has already been programmed at 0. |
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