TMP86CS25AFG datasheet(63/194 Pages) TOSHIBA

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Page 53

TMP86CS25AFG

5. I/O Ports

The TMP86CS25AFG have 6 parallel input/output ports (42 pins) as follows.

Each output port contains a latch, which holds the output data. All input ports do not have latches, so the external

input data should be externally held until the input data is read from outside or reading should be performed several

timer before processing. Figure 5-1 shows input/output timing examples.

External data is read from an I/O port in the S1 state of the read cycle during execution of the read instruction. This

timing cannot be recognized from outside, so that transient input such as chattering must be processed by the pro-

gram.

Output data changes in the S2 state of the write cycle during execution of the instruction which writes to an I/O

port.

Note: The positions of the read and write cycles may vary, depending on the instruction.

Figure 5-1 Input/Output Timing (Example)

Primary Function

Secondary Functions

Port P1

8-bit I/O port

External interrupt input, serial interface input/output, UART input/output

and segment output.

Port P2

3-bit I/O port

Low-frequency resonator connections, external interrupt input, STOP

mode release signal input.

Port P3

7-bit I/O port

Timer/Counter input/output and divider output and segment/common

output.

Port P5

8-bit I/O port

Segment output.

Port P6

8-bit I/O port

Analog input, external interrupt input, timer/counter input and STOP

mode release signal input.

Port P7

8-bit I/O port

Common output. Timer/Counter input/output and divider output.

Instruction execution cycle

Input strobe

Data input

Ex: LD A, (x)

Fetch cycle

Read cycle

S0 S1 S2 S3 S0 S1 S2 S3 S0 S1 S2 S3

Instruction execution cycle

Output strobe

Old

New

Data output

Ex: LD (x), A

Fetch cycle

Write cycle

S0 S1 S2 S3 S0 S1 S2 S3 S0 S1 S2 S3

(a) Input timing

(b) Output timing

TMP86CS25AFG Datasheet(PDF) 63 Page - Toshiba Semiconductor

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