STM32U375CEU6QTR datasheet(40/222 Pages) STMICROELECTRONICS

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•

Configurable I/O polarity

•

Encoder mode

•

Repetition counter

•

Up to 2 independent channels for:

–

Input capture

–

PWM generation (edge-aligned mode)

–

One-pulse mode output

•

Interrupt generation on 10 events

•

DMA request generation on the following events:

–

Update event

–

Input capture

3.30.5

Infrared interface

An infrared interface (IRTIM) for remote control is available on the device. It can be used with an infrared LED to

perform remote control functions. It uses internal connections with USART1, UART4, TIM16, and TIM17.

3.30.6

Independent watchdog (IWDG)

The independent watchdog (IWDG) peripheral offers a high safety level, thanks to its capability to detect

malfunctions due to software or hardware failures.

The IWDG is clocked by an independent clock, and stays active even if the main clock fails. In addition, the

watchdog function is performed in the VDD voltage domain, allowing the IWDG to remain functional even in low-

power modes.

The IWDG is best suited for applications that require the watchdog to run as a totally independent process outside

the main application, making it very reliable to detect any unexpected behavior.

The main features of IWDG are:

•

12-bit down-counter

•

Dual voltage domain, thus enabling operation in low-power modes

•

Independent clock

•

Early wake-up interrupt generation

•

Reset generation

–

In case of timeout

–

In case of refresh outside the expected window

3.30.7

Window watchdog (WWDG)

The system window watchdog (WWDG) is used to detect the occurrence of a software fault, usually generated by

external interference or by unforeseen logical conditions, which causes the application program to abandon its

normal sequence.

The watchdog circuit generates a device reset on expiry of a programmed time period, unless the program

refreshes the contents of the down-counter before the T6 bit becomes cleared.

A device reset is also generated when the 7-bit down-counter value (in the control register) is refreshed before the

down-counter reaches the window register value. This implies that the counter must be refreshed within a limited

window.

The WWDG clock is prescaled from the APB clock and has a configurable time window that can be programmed

to detect abnormally late or early application behavior.

The WWDG is best suited for applications that require the watchdog to react within an accurate timing window.

The main features of WWDG are:

•

Programmable free-running down-counter

•

Conditional reset:

–

Reset (if WWDG activated) when the down-counter value becomes lower than 0x40

–

Reset (if WWDG activated) if the down-counter is reloaded outside the window

•

Early wake-up interrupt (EWI) (if enabled and WWDG activated) when the down-counter is equal to 0x40

STM32U375xx

Functional overview

DS14861 - Rev 2

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