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AX88780 Datasheet(PDF) 26 Page - ASIX Electronics Corporation

Part # AX88780
Description  High-Performance Non-PCI Single-Chip 32-bit 10/100M Fast Ethernet Controller
PDF  55 Pages
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Manufacturer  ASIX [ASIX Electronics Corporation]
Direct Link  http://www.asix.com.tw
Logo ASIX - ASIX Electronics Corporation

AX88780 Datasheet(HTML) 26 Page - ASIX Electronics Corporation

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AX88780
26
ASIX ELECTRONICS CORPORATION
4.21 RXBTHD1--RX Buffer Threshold1 Register
Offset Address= 0xFC5C
Default = 0x0000_0600
Field
Name
Type
Default
Description
31:11
-
R
All 0’s
Reserved
10:0
RXHIGHB
R/W
0x600
RX Remainder Capacity Upper-Bound
This field defines as upper bound of remainder size of RX buffer for pause
operation. If the flow control is enabled, MAC will stop to send pause
frame until the available space of receive buffer is more than this value.
The unit is 16-byte.
4.22 RXFULTHD--RX Buffer Full Threshold Register
Offset Address= 0xFC60
Default = 0x0000_0100
Field
Name
Type
Default
Description
31:11
-
R
All 0’s
Reserved
10:0
RXFULB
R/W
0x100
RX Full Threshold
This field defines the least capacity of RX buffer. AX88780 will cause RX
full if it remains capacity less than this value. The unit is 16-byte.
4.23 MISC—Misc. Control Register
Offset Address= 0xFC68
Default = 0x0000_0013
Field
Name
Type
Default
Description
31:6
-
R
All 0’s
Reserved
5
WAKE_LNK
R/W
0
WAKE-UP by Link-Up Function
If this bit is enabled, MAC will drive wakeup pin whenever there is link-up
occurrence. The polarity of wakeup pin is according to bit0 of CMD
register.
1= enable
0= disable
4
WAKE_MAG
R/W
1
WAKE-UP by Magic Packet
If this bit is enabled, MAC will drive wakeup pin whenever there is magic
packet detected by hardware. The polarity of wakeup pin is according to
bit0 of CMD register.
1= enable wake-up by magic packet
0 = disable
3:2
-
R/W
00
Reserved
1
SRST_PHY
R/W
1
Software Reset Internal PHY
Driver set this bit to ‘0’ to reset internal PHY. The reset duration is
depended on whenever this bit is de-asserted by deriver.
1 = in normal operation
0 = in reset status
0
SRST_MAC
R/W
1
Software Reset MAC
Driver set this bit to ‘0’ to reset MAC. The reset duration is depended on
whenever this bit is de-asserted by deriver. After power-on, driver must
activate software reset MAC once before initial other registers.
1 = in normal operation
0 = in reset status



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