ASIX ELECTRONICS CORPORATION

11

AX88772

USB to 10/100 Fast Ethernet/HomePNA Controller

communicating with multiple PHY devices at the same time by identifying the managed PHY with 5-bit, unique Phy ID.

The Phy ID of the embedded 10/100 Ethernet PHY is being pre-assigned to “1_0000”.

Figure 4 shows the internal control mux for the station management interface. When doing read, the “mdin” signal will be

driven from 10/100 Ethernet PHY only if Phy ID matches with “1_0000”, otherwise, it will always be driven from

external MDIO pin of the ASIC.

Figure 4: Internal Control Mux for Station Management Interface

3.5 Memory Arbiter

The memory arbiter block is responsible for storing received MAC frames into on-chip SRAM (packet buffer) and then

forwarding to USB bus upon request from USB host via bulk in transfer. It also monitors packet buffer usage in

full-duplex mode for triggering PAUSE frame transmission out on TX direction. The memory arbiter block is also

responsible for storing MAC frames received from USB host via bulk out transfer and waiting to be transmitted out

towards Ethernet network.

3.6 USB to Ethernet Bridge

The USB to Ethernet bridge block is responsible for converting Ethernet MAC frame into USB packets or vice-versa.

This block supports proprietary burst transfer mechanism (submitted for US patent application) to offload software

burden and to offer very high packet transfer throughput over USB bus.

3.7 Serial EEPROM Loader

The serial EEPROM loader is responsible for reading configuration data automatically from external serial EEPROM

after power-on reset.

3.8 General Purpose I/O

There are 3 general purpose I/O pins provided by this ASIC.

STA

10/100 Ethernet

PHY

Phy ID = 1_0000

MDC

MDIO

mdin

mdout