ADF4378 datasheet(39/84 Pages) AD

39 / 84 page

Data Sheet

ADF4378

APPLICATIONS INFORMATION

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Rev. A | 39 of 84

PFD

Cycles=fPFD×5/2×π×LPBW =250

MHz×5/2×π×

460 kHz =432

The calculated minimum PFD cycle count of 432 is then compared

to the PFD cycle column in Table 14, which results in 542 PFD

cycles and LD_COUNT = 9.

To determine the LDWIN_PW setting from Table 16, calculate tIDEL

from Equation 10 or Equation 11. Because the BLEED_I bit fields,

Bits[9:0], is set to 0 in the Reference to Output Propagation Delay

Settings section, tIDEL = 0. Based on Table 16, when tIDEL = 0,

LDWIN_PW is set to 0. The RST_LD bit is related to the lock

detector and is set to 0 in normal use cases.

Table 28. SPI Summary, Lock Detector

Bit Field

Value

EN_LOL

0x1

EN_LDWIN

0x1

LD_COUNT

0x9

LDWIN_PW

0x0

RST_LD

0x0

VCO Automatic Calibration Settings

The procedure to determine the SPI registers for an automatic VCO

calibration is outlined in the VCO Calibration section.

The VCO calibration Step 1 enables the automatic calibration

bit, EN_AUTOCAL, along with enabling several VCO calibration

dividers, clocks, and the temperature sensor.

Table 29. SPI Summary, VCO Automatic Calibration, Step 1

Bit Field

Value

EN_DNCLK

0x1

EN_DRCLK

0x1

ADC_CLK_SEL

0x0

ADC_A_CONV

0x1

EN_AUTOCAL

0x1

EN_ADC_CNV

0x1

EN_ADC

0x1

EN_ADC_CLK

0x1

PD_ADC

0x0

In VCO calibration Step 2, Table 17 determines the state of

CAL_CT_SEL, DCLK_DIV2, and DCLK_MODE based off the 250

MHz PFD frequency. DCLK_DIV1 must always be set to 1 regard-

less of PFD frequency. Table 17 provides an equation to calculate

fDIV_RCLK:

fDIV_RCLK=fPFD/2

= 250 MHz/2 = 125 MHz

Table 30. SPI Summary, VCO Automatic Calibration, Step 2

Bit Field

Value

CAL_CT_SEL

0x1

Table 30. SPI Summary, VCO Automatic Calibration, Step 2 (Continued)

Bit Field

Value

DCLK_DIV2

0x0

DCLK_MODE

0x1

DCLK_DIV1

0x1

In the VCO calibration Step 3 and Step 4, Equation 13,

Equation 14, Equation 15, and Equation 16 are provided

to calculate the SYNTH_LOCK_TIMEOUT bit fields, Bits[14:0],

VCO_ALC_TIMEOUT bit fields, Bits[14:0], VCO_BAND_DIV bits,

and ADC_CLK_DIV bits from fDIV_RCLK.

SYNTH_LOCK_TIMEOUT≥Ceiling

200 μs × 125 MHz =25000

VCO_ALC_TIMEOUT≥Ceiling

50 μs × 125 MHz

=6250

VCO_BAND_DIV≥Ceiling 15 μs × 125 MHz

16×21

=Ceiling58.59375 =59

ADC_CLK_DIV>Ceiling 125 MHz

400 kHz−2

=Ceiling

77.625 =78

Table 31. SPI Summary, VCO Automatic Calibration, Step 3 and Step 4

Bit Field

Value

SYNTH_LOCK_TIMEOUT

0x61A8

VCO_ALC_TIMEOUT

0x186A

VCO_BAND_DIV

0x3B

ADC_CLK_DIV

0x4E

SYSREF Input Settings

To use SYSREF retimer path, R_DIV value must be equal to 1.

EN_RDBLR may be enabled. Maximum input reference frequency

is 500 MHz while EN_RDBLR bit is 0. If EN_RDBLR bit is set to 1,

maximum reference frequency is limited to 250 MHz.

The SYSREF input buffer type can be selected by SR_SEL bit in

REG0042. SR_SEL = 0, which sets the ADF4378 SYSREF input

buffer for CML/LVPECL operation. Internal common mode voltage

is set to 1.85 V. SR_SEL = 1, which sets the input buffer for a

generic LVDS input. Internal common mode voltage is set to 1.3 V.

Table 32. SPI Summary, SYSREF Input Settings

Bit Field

Value

R_DIV

0x01

EN_RDBLR

0x01 for input reference frequency <250

or 0x00

SR_SEL

0x00 for CML/LVPECL operation, 0x01

for LVDS operation

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