ADF4378 datasheet(42/84 Pages) AD

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Data Sheet

ADF4378

APPLICATIONS INFORMATION

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Rev. A | 42 of 84

Due to the controlled tPD of the ADF4378 devices, it is reasona-

ble to expect that a significant portion of the total system skew

(tSKEW_SYSTEM) is due to propagation delay mismatches in traces or

cables (tSKEW_B, tSKEW_D), and skew in other components (tSKEW_A)

or instruments (tMEAS_ERROR). Figure 99 and Equation 24 provide

several sources of possible output skew error in a typical system.

The Clock Skew in Large Multi-GHz Clock Trees article outlines

the skew trade-offs in component selection, board design, and

end-user cost requirements in large clock trees.

Figure 99. Total System Skew

tSKEW_SYSTEM=tSKEW_A+tSKEW_B+tSKEW_C

+tSKEW_D+tMEAS_ERROR

(24)

where:

tSKEW_A = tA1 − tA0

tSKEW_B = tPD_B1 − tPD_B0

tSKEW_C = tPD_C1 − tPD_C0

tSKEW_D = tPD_D1 − tPD_D0

tMEAS_ERROR = tCHAN1 − tCHAN2

To further minimize clock skew between multiple clocks, the

ADF4378 devices provide SPI programmable adjustments to in-

crease or decrease the tPD in sub-ps steps. Table 39 and Table

40 provide a comparison of the multiple reference to output delay

controls. In large clock trees, these tPD adjustments can alleviate

output-to-output skew trade-offs in component selection, board

design, and end-user cost requirements.

Table 39. ADF4378 Reference to Output Delay Control Comparison

Parameters

Referenc

e Delay

Feedback

Delay

Charge-Pump Bleed

Current

Output Invert

N_DEL

EN_BLEED,

BLEED_I bit fields,

Bits[9:0],

BLEED_POL

INV_CLKOUT

tPD

Increases Decreases BLEED_

POL = 0,

increases

BLEED_

POL = 1,

decrease

Inverts output,

see Table 19

Number of

Steps

127

1023

Step Size

~1 ps

~0.01 ps to 65 ps,

varies with CP_I and

fPFD Equation 9

1 2×fOUT

Table 40. ADF4378 Reference to Output Typical Performance Impact

Parameters

Reference and

Feedback Delay

Charge-Pump

Bleed Current

Output Invert

Temperature

Coefficient

Minimal, Figure

18 and Figure 23

None, Figure 21

and Figure 24

None

LNORM

<1 dB, Figure 45

<1 dB, Figure 42

None

L1/f

<1 dB, Figure 45

<4 dB, Figure 42

None

Spurious

Minimal

fPFD ≥ 50 MHz:

minimal, fPFD < 50

MHz, contact ADI

Minimal

Lock Detector

None

For more

information, see

the Lock Detector

section

None

Figure 45 and Figure 43 show a general trend that an increasing

magnitude of R_DEL, N_DEL, or BLEED_I bit fields, Bits[9:0] caus-

es a small increase in LNORM and L1/f . Increases in LNORM and L1/f

result in clock jitter (see Figure 12 and Figure 15). Therefore, in the

most performance sensitive applications, identifying ways to mini-

mize the magnitude of the R_DEL, N_DEL, or BLEED_I bit fields,

Bits[9:0] values is required. As an example, Figure 100 provides

two skew adjustment methods to minimize the skew in Figure 99.

Method 1 only adjusts one of the reference to output delay adjust-

ments provided in Table 39. Method 1 results in an R_DEL, N_DEL,

or BLEED_I bit fields, Bits[9:0] maximum adjustment equal to half

an output cycle, or 1/(2 × fOUT). Method 2 minimizes the magnitude

of R_DEL, N_DEL, or BLEED_I bit fields, Bits[9:0] by utilizing the

output invert along with either R_DEL, N_DEL, or BLEED_I bit

fields, Bits[9:0] adjustments. When compared to Method 1, Method

2 results in a lower R_DEL, N_DEL, or BLEED_I bit fields, Bits[9:0]

maximum adjustment of a quarter cycle output cycle, or 1/(4 ×

fOUT). Method 2 is furthered described in Table 41.

Figure 100. Skew Adjustment Methods

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