ISL70001SEH datasheet(17/24 Pages) RENESAS

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ISL70001SEH, ISL70001SRH

FN7956 Rev 3.03

Page 17 of 23

Feb 5, 2024

Derating Current Capability

Most space programs issue specific derating guidelines for parts,

but these guidelines take the pedigree of the part into account.

For instance, a device built to MIL-PRF-38535, such as the

ISL70001SEH, ISL70001SRH, is already heavily derated from a

current density standpoint. However, a mil-temp or commercial

IC that is up-screened for use in space applications may need

additional current derating to ensure reliable operation because

it was not built to the same standards as the ISL70001SEH,

ISL70001SRH.

Figure 12 on page 17 shows the maximum average output

current of the ISL70001SEH, ISL70001SRH with respect to

junction temperature. These plots take into account the worst-

case current share mismatch in the power blocks and the current

density requirement of MIL-PRF-38535 (< 2 x 105 A/cm2). The

plot clearly shows that the ISL70001SEH, ISL70001SRH can

handle 12.1A at +125°C from a worst-case current density

standpoint, but the part is limited to 7.8A because that is the

lower limit of the current limit threshold with all six power blocks

connected.

PCB Design

PCB design is critical to high-frequency switching regulator

performance. Careful component placement and trace routing

are necessary to reduce voltage spikes and minimize

undesirable voltage drops. Selection of a suitable thermal

interface material is also required for optimum heat dissipation

and to provide lead strain relief. See Table 1 on page 19 for

layout x-y coordinates.

PCB Plane Allocation

Four layers of 2-ounce copper are recommended. Layer 2 should

be a dedicated ground plane with all critical component ground

connections made with vias to this layer. Layer 3 should be a

dedicated power plane split between the input and output power

rails. Layers 1 and 4 should be used primarily for signals but can

also provide additional power and ground islands, as required.

PCB Component Placement

Components should be placed as close as possible to the IC to

minimize stray inductance and resistance. Prioritize the

placement of bypass capacitors on the pins of the IC in the order

shown: REF, SS, AVDD, DVDD, PVINx (high frequency capacitors),

EN, PGOOD, PVINx (bulk capacitors).

Locate the output voltage resistive divider as close as possible to

the FB pin of the IC. The top leg of the divider should connect

directly to the POL (Point of Load), and the bottom leg of the

divider should connect directly to AGND. The junction of the

resistive divider should connect directly to the FB pin.

Locate a Schottky clamp diode as close as possible to the LXx

and PGNDx pins of the IC. A small series R-C snubber connected

from the LXx pins to the PGNDx pins may be used to damp high

frequency ringing on the LXx pins, if desired, see Figure 13.

PCB Layout

Use a small island of copper to connect the LXx pins of the IC to

the output inductor on Layers 1 and 4. To minimize capacitive

coupling to the power and ground planes, void the copper on

Layers 2 and 3 adjacent to the island. Place most of the island of

Layer 4 to minimize the amount of copper that must be voided

from the ground plane (Layer 2).

Keep all other signal traces as short as possible.

For an example layout, see AN1518.

Thermal Management for Ceramic Package

For optimum thermal performance, place a pattern of vias and a

thermal land on the top layer of the PCB directly underneath the

IC. Connect the vias to the plane, which serves as a heatsink. To

ensure good thermal contact, thermal interface material such as

a Sil-Pad or thermally conductive epoxy should be used to fill the

gap between the vias and the bottom of the ceramic package.

Lead Strain Relief

The package leads protrude from the bottom of the package and

the leads need forming to provide strain relief. On the ceramic

bottom package R48.A, the Sil-pad or epoxy maybe be used to fill

the gap left between the PCB board and the bottom of the

package when lead forming is completed. On the heat sink

option of the package, R48.B, the lead forming should be made

so that the bottom of the heatsink and the formed leads are

flush.

12.14

10.18

8.57

7.25

6.16

5.3

120

125

130

135

140

145

150

155

JUNCTION TEMPERATURE (°C)

MINIMUM OCP

LEVEL = 7.8A

6A AT +146°C

FIGURE 12. CURRENT vs TEMPERATURE

FIGURE 13. SCHOTTKY DIODE AND R-C SNUBBER

COUT

LOUT

VOUT

LXx

VREF

ERROR

AMPLIFIER

REF

CREF

PGNDx

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