P240 datasheet(84/348 Pages) ALTERA

84 / 348 page

5–24

Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family

PLL Cascading

Cyclone III Device Handbook

December 2011

Altera Corporation

Volume 1

Figure 5–18 shows an example of phase shift insertion using fine resolution through

VCO phase taps method. The eight phases from the VCO are shown and labeled for

reference. In this example, CLK0 is based on 0° phase from the VCO and has the C

value for the counter set to one. The CLK1 signal is divided by four, two VCO clocks

for high time and two VCO clocks for low time. CLK1 is based on the 135° phase tap

from the VCO and has the C value for the counter set to one. The CLK1 signal is also

divided by four. In this case, the two clocks are offset by 3

Φfine. CLK2 is based on the

0° phase from the VCO but has the C value for the counter set to three. This creates a

delay of two

Φcoarse (two complete VCO periods).

You can use the coarse and fine phase shifts to implement clock delays in the

Cyclone III device family.

The Cyclone III device family supports dynamic phase shifting of VCO phase taps

only. The phase shift is configurable for any number of times. Each phase shift takes

about one scanclk cycle, allowing you to implement large phase shifts quickly.

PLL Cascading

Two PLLs are cascaded to each other through the clock network. If your design

cascades PLLs, the source (upstream) PLL must have a low-bandwidth setting, while

the destination (downstream) PLL must have a high-bandwidth setting.

Figure 5–18. Delay Insertion Using VCO Phase Output and Counter Delay Time

td0-1

td0-2

1/8 tVCO

tVCO

135

180

225

270

315

CLK0

CLK1

CLK2

P240 Datasheet(PDF) 84 Page - Altera Corporation