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FS32K112BFT0M Datasheet(PDF) 41 Page - NXP Semiconductors |
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FS32K112BFT0M Datasheet(HTML) 41 Page - NXP Semiconductors |
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41 / 85 page  Table 26. QuadSPI electrical specifications (continued) FLASH PORT Sym Unit FLASH A FLASH B RUN1 HSRUN1 RUN/HSRUN2 QuadSPI Mode SDR SDR SDR DDR3 Internal Sampling Internal DQS Internal Sampling Internal DQS Internal Sampling External DQS N1 PAD Loopback Internal Loopback N1 PAD Loopback Internal Loopback N1 External DQS Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max SCK Duty Cycle tSDC ns Data Input Setup Time tIS ns 15 - 2.5 - 10 - 14 - 1.6 - 9 - 25 - 2 - Data Input Hold Time tIH ns 0 - 1 - 1 - 0 - 1 - 1 - 0 - 20 - Data Output Valid Time tOV ns - 4.5 - 4.5 - 4.5 - 4 - 4 - 4 - 10 - 10 Data Output In-Valid Time tIV ns - 5 - 5 - 5 - 5 - 35 - 5 - 5 5 - CS to SCK Time 6 tCSSCK ns 5 - 5 - 5 - 5 - 5 - 5 - 10 - 10 - SCK to CS Time 7 tSCKCS ns 5 - 5 - 5 - 5 - 5 - 5 - 5 - 5 - Output Load pf 25 25 25 25 25 25 25 25 1. See Reference Manual for details on mode settings 2. See Reference Manual for details on mode settings 3. Valid for HyperRAM only 4. RWDS(External DQS CLK) frequency 5. For operating frequency ≤ 64 Mhz,Output invalid time is 5 ns. 6. Program register value QuadSPI_FLSHCR[TCSS] = 4`h2 7. Program register value QuadSPI_FLSHCR[TCSH] = 4`h1 |
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