CD54HC646, CD74HCT646

OCTAL BUS TRANSCEIVERS AND REGISTERS

WITH 3-STATE OUTPUTS

SCHS278B – APRIL 2003 – REVISED APRIL 2003

1

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

D 2-V to 6-V VCC Operation (CD54HC646)

D 4.5-V to 5.5-V VCC Operation (CD74HCT646)

D Wide Operating Temperature Range of

–55

°C to 125°C

D Balanced Propagation Delays and

Transition Times

D Standard Outputs Drive Up To 15 LS-TTL

Loads

D Significant Power Reduction Compared to

LS-TTL Logic ICs

D Inputs Are TTL-Voltage Compatible

(CD74HCT646)

D Independent Registers for A and B Buses

D Multiplexed Real-Time and Stored Data

D True Data Paths

description/ordering information

The CD54HC646 and CD74HCT646 consist of bus-transceiver circuits with 3-state outputs, D-type flip-flops,

and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal

registers. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate

clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can

be performed with these devices.

Output-enable (OE) and direction-control (DIR) inputs control the transceiver functions. In the transceiver

mode, data present at the high-impedance port can be stored in either or both registers.

The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. DIR

determines which bus receives data when OE is active (low). In the isolation mode (OE high), A data can be

stored in one register and /or B data can be stored in the other register.

When an output function is disabled, the input function still is enabled and can be used to store data. Only one

of the two buses, A or B, can be driven at a time.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

ORDERING INFORMATION

TA

PACKAGE†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

55

°Cto125°C

SOIC – M

Tape and reel

CD74HCT646M96

HCT646M

–55

°C to 125°C

CDIP – F

Tube

CD54HC646F3A

CD54HC646F3A

† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design

guidelines are available at www.ti.com/sc/package.

Copyright

 2003, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

CLKAB

SAB

DIR

A1

A2

A3

A4

A5

A6

A7

A8

GND

VCC

CLKBA

SBA

OE

B1

B2

B3

B4

B5

B6

B7

B8

1

2

3

4

5

6

7

8

9

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13

CD54HC646 ...F PACKAGE

CD74HCT646 ...M PACKAGE

(TOP VIEW)

On products compliant to MIL-PRF-38535, all parameters are tested

unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.