LTC2450-1

11

24501fb

Examples of Aborting Cycle using CS

For some applications the user may wish to abort the I/O

cycle and begin a new conversion. If the LTC2450-1 is in

the data output state, a CS rising edge clears the remaining

data bits from memory, aborts the output cycle and triggers

a new conversion. Figure 9 shows an example of aborting

an I/O with idle-high (CPOL = 1) and Figure 10 shows an

example of aborting an I/O with idle-low (CPOL = 0).

A new conversion cycle can be triggered using the CS

signal without having to generate any serial clock pulses

as shown in Figure 11. If SCK is maintained at a LOW

logic level, after the end of a conversion cycle, a new

conversion operation can be triggered by pulling CS low

and then high. When CS is pulled low (CS = LOW), SDO

will output the most significant bit (D15) of the result of

the just completed conversion. While a low logic level is

maintained at SCK pin and CS is subsequently pulled high

(CS = HIGH) the remaining 15 bits of the result (D14:D0)

are discarded and a new conversion cycle starts.

Following the aborted I/O, additional clock pulses in the

CONVERT state are acceptable, but excessive signal tran-

sitions on SCK can potentially create noise on the ADC

during the conversion, and thus may negatively influence

the conversion accuracy.

APPLICATIONS INFORMATION

Figure 8. Idle-Low (CPOL = 0) Clock. The 16th SCK Falling Edge Triggers a New Conversion

Figure 7. Idle-Low (CPOL = 0) Clock. ⎯C⎯S Triggers a New Conversion

SCK

SD0

CONVERT

CONVERT

SLEEP

DATA OUTPUT

24501 F07

CS

SD0

SCK

CONVERT

CONVERT

SLEEP

DATA OUTPUT

24501 F08

CS