ADC14DS080

SNAS428B – SEPTEMBER 2007 – REVISED APRIL 2013

www.ti.com

TEST

When this signal is asserted high, a fixed test pattern (10100110001110 msb->lsb) is sourced at the data

outputs. When low, the ADC is in normal operation. The user may specify a custom test pattern via the serial

control interface.

NOTE

This signal has no effect when SPI_EN is high and the SPI interface is enabled.

WAM

In dual-lane mode only, when this signal is at logic-0 the serial data words are offset by half-word. With this

signal at logic-1 the serial data words are aligned with each other. In single lane mode this pin must be set to

logic-0.

NOTE

This signal has no effect when SPI_EN is high and the SPI interface is enabled.

SPI_EN

The SPI interface is enabled when this signal is asserted high. In this case the direct control pins (OF/DCS,

PD_A, PD_B, DLC, WAM, TEST) have no effect. When this signal is deasserted, the SPI interface is disabled

and the direct control pins are enabled.

SCSb, SDI, SCLK

These pins are part of the SPI interface. See Serial Control Interface for more information.

DIGITAL OUTPUTS

Digital outputs consist of six LVDS signal pairs (SD0_A, SD1_A, SD0_B, SD1_B, OUTCLK, FRAME) and CMOS

logic outputs ORA, ORB, DLL_Lock, and SDO.

LVDS Outputs

The digital data for each channel is provided in a serial format. Two modes of operation are available for the

serial data format. Single-lane serial format (shown in Figure 2 ) uses one set of differential data signals per

channel. Dual-lane serial format (shown in Figure 3) uses two sets of differential data signals per channel in

order to slow down the data and clock frequency by a factor of 2. At slower rates of operation (typically below 65

MSPS) the single-lane mode may the most efficient to use. At higher rates the user may want to employ the

dual-lane scheme. In either case DDR-type clocking is used. For each data channel, an overrange indication is

also provided. The OR signal is updated with each frame of data.

ORA, ORB

These CMOS outputs are asserted logic-high when their respective channel’s data output is out-of-range in

either high or low direction.

DLL_Lock

When the internal DLL is locked to the input CLK, this pin outputs a logic high. If the input CLK is changed

abruptly, the internal DLL may become unlocked and this pin will output a logic low. Cycle Reset_DLL to re-lock

the DLL to the input CLK.

SDO

This pin is part of the SPI interface. See Serial Control Interface for more information.

24

Submit Documentation Feedback

Copyright © 2007–2013, Texas Instruments Incorporated

Product Folder Links: ADC14DS080