ADS5271 datasheet(14/42 Pages) TI2

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D15 D14 D13 D12 D11 D10 D9

D8 D7 D6 D5 D4 D3 D2 D1 D0

A7 A6 A5 A4 A3 A2 A1 A0

SCLK

SDATA

DatalatchedonrisingedgeofSCLK

StartSequence

EndSequence

ADS5287

SBAS428D – JANUARY 2008 – REVISED JUNE 2012

www.ti.com

SERIAL INTERFACE

The ADS5287 has a set of internal registers that can be accessed through the serial interface formed by pins CS

(chip select, active low), SCLK (serial interface clock), and SDATA (serial interface data). When CS is low, the

following actions occur:

•

Serial shift of bits into the device is enabled

•

SDATA (serial data) is latched at every rising edge of SCLK

•

SDATA is loaded into the register at every 24th SCLK rising edge

If the word length exceeds a multiple of 24 bits, the excess bits are ignored. Data can be loaded in multiples of

24-bit words within a single active CS pulse. The first eight bits form the register address and the remaining 16

bits form the register data. The interface can work with SCLK frequencies from 20MHz down to very low speeds

(a few hertz) and also with a non-50% SCLK duty cycle.

After power-up, the internal registers must be initialized to the respective default values. Initialization can be

done in one of two ways:

1. Through a hardware reset, by applying a low-going pulse on the RESET pin; or

2. Through a software reset; using the serial interface, set the RST bit high. Setting this bit initializes the

internal registers to the respective default values and then self-resets the RST bit low. In this case, the

RESET pin stays high (inactive).

SERIAL INTERFACE TIMING

ADS5287

PARAMETER

DESCRIPTION

MIN

TYP

MAX

UNIT

SCLK period

SCLK high time

SCLK low time

Data setup time

Data hold time

CS fall to SCLK rise

Time between last SCLK rising edge to CS rising edge

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