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DAC8802IPWR Datasheet(PDF) 3 Page - Texas Instruments |
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DAC8802IPWR Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 24 page ![]() www.ti.com ELECTRICAL CHARACTERISTICS (1) DAC8802 SBAS351B – AUGUST 2005 – REVISED FEBRUARY 2007 V DD = 2.7 V to 5.5 V, IOUTX = Virtual GND, AGNDX = 0 V, VREFA, B = 10 V, TA = full operating temperature range, unless otherwise noted. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT STATIC PERFORMANCE(2) Resolution 14 Bits Relative accuracy INL ±1 LSB Differential nonlinearity DNL ±1 LSB Data = 0000h, TA = 25°C 10 nA Output leakage current IOUTX Data = 0000h, TA = TA max 20 nA Full-scale gain error GFSE Data = 3FFFh ±0.75 ±4 mV Full-scale tempco(3) TCVFS 1 ppm/ °C Feedback resistor RFBX VDD = 5 V 5 k Ω REFERENCE INPUT(3) VREFX Range VREFX –15 15 V Input resistance RREFX 4 5 6 k Ω Input resistance match RREFX Channel-to-channel 1 % Input capacitance CREFX 5 pF ANALOG OUTPUT(3) Output current IOUTX Data = 3FFFh 1.6 2.5 mA Output capacitance COUTX Code-dependent 50 pF LOGIC INPUTS(3) VDD = 2.7 V 0.6 V Input low voltage VIL VDD = 5 V 0.8 V VDD = 2.7 V 2.1 V Input high voltage VIH VDD = 5 V 2.4 V Input leakage current IIL 1 µA Input capacitance CIL 10 pF INTERFACE TIMING (4) Clock width high tCH 10 ns Clock width low tCL 10 ns CS to Clock setup tCSS 0 ns Clock to CS hold tCSH 10 ns Clock to SDO prop delay tPD 2 20 ns Load DAC pulsewidth tLDAC 20 ns Data setup tDS 10 ns Data hold tDH 10 ns Load setup tLDS 5 ns Load hold tLDH 25 ns (1) Specifications subject to change without notice. (2) All static performance tests (except IOUT) are performed in a closed-loop system using an external precision OPA277 I-to-V converter amplifier. The DAC8802 RFB terminal is tied to the amplifier output. Typical values represent average readings measured at +25°C. (3) These parameters are specified by design and not subject to production testing. (4) All input control signals are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. 3 Submit Documentation Feedback |
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