LM48557

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SNAS486D – JULY 2009 – REVISED MAY 2013

VOLUME CONTROL

The LM48557 has a 64 step volume control, but only 36 steps are recommended for use. Use steps 1 through

32 and steps 61 through 64 to set the gain of the device. Accessing steps 33 through 60 results in the repeated

gain conditions shown in Table 7. Steps 33 through 60 are not tested and should not be used.

SHUTDOWN FUNCTION

The LM48557 features a low-power shutdown mode that disables the device lowers the quiescent current to

0.01µA. Set bit B0 (SHDN) of the Mode Control register to 0 to disable the amplifier and charge pump. Set

SHDN to 1 for normal operation. Shutdown mode does not clear the I2C register. When re-enabled, the device

returns to its previous volume setting. To clear the I2C register, either remove power from the device, or toggle

RESET (see RESET section).

RESET

The LM48557 features an active low reset input. Driving RESET low clears the I2C register. Volume control is set

to 000000 (-90dB) and SHDN is set to 0, disabling the device. While RESET is low, the LM48557 ignores any

I2C data. After the device is reset, and RESET is driven high, the LM48557 remains in shutdown mode with the

volume set to -90dB. Re-enable the device by writing to the I2C register.

MUTE

The LM48557 features a mute mode. Set bit B1 (MUTE) of the Mode Control register to 1 to mute the device. In

mute mode, the gain is set to -90dB, equivalent to the volume step 1. Set MUTE = 0 to unmute the device. Once

unmuted, the device returns to its previous volume step.

TEST MODE

If enabled, TESTMODE does not affect device performance under normal operating conditions. Operating above

the recommended supply voltage range with TESTMODE enabled can result in damage to the device.

PROPER SELECTION OF EXTERNAL COMPONENTS

Power Supply Bypassing/Filtering

Proper power supply bypassing is critical for low noise performance and high PSRR. Place the supply bypass

capacitors as close to the device as possible. Place a 1µF ceramic capacitor from VDD to GND. Additional bulk

capacitance may be added as required.

Charge Pump Capacitor Selection

Use low ESR ceramic capacitors (less than 100m

Ω) for optimum performance.

Charge Pump Flying Capacitor (C1)

The flying capacitor (C1) affects the load regulation and output impedance of the charge pump. A C1 value that

is too low results in a loss of current drive, leading to a loss of amplifier headroom. A higher valued C1 improves

load regulation and lowers charge pump output impedance to an extent. Above 2.2µF, the RDS(ON) of the charge

pump switches and the ESR of C1 and C2 dominate the output impedance. A lower value capacitor can be used

in systems where low maximum output power requirements.

Charge Pump Hold Capacitor (C2)

The value and ESR of the hold capacitor (C2) directly affects the ripple on CPVSS. Increasing the value of C2

reduces output ripple. Decreasing the ESR of C2 reduces both output ripple and charge pump output impedance.

A lower value capacitor can be used in systems where low maximum output power requirements.

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