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PCM1737E/2K.B Datasheet(PDF) 13 Page - Texas Instruments |
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PCM1737E/2K.B Datasheet(HTML) 13 Page - Texas Instruments |
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13 / 32 page  ® 13 PCM1737 50% of V DD 50% of V DD 50% of V DD 50% of V DD ML MC MDI MDO t MLS t MCH t MCY t MOS t MDS t MDI t MCL t MHH t MLH LSB LSB SYMBOL PARAMETER MIN MAX UNITS tMCY MC Pulse Cycle Time 100 ns tMCL MC Low Level Time 50 ns tMCH MC High Level Time 50 ns tMHH ML High Level Time 300 ns tMLS ML Falling Edge to MC Rising Edge 20 ns tMLH ML Hold Time(1) 20 ns tMDI Hold Time 15 ns tMDS MDL Set Up Time 20 ns tMOS MC Falling Edge to MDSO Stable 30 ns NOTE: (1) MC rising edge for LSB to ML rising edge. FIGURE 10. Control Interface Timing. Figure 8 details the Read operation. First, Control Register 21 must be written with the index of the register to be read back. In addition, the INC bit must be set to logic ‘0’ in order to disable the auto-increment read function. The Read cycle is then initiated by setting ML to logic ‘0’ and setting the R/W bit of the control data word to logic ‘1’, indicating a Read operation. MDO remains at a high impedance state until the last 8 bits of the 16-bit read cycle, which corre- sponds to the 8 data bits of the register indexed by the REG[6:0] bits of Control Register 21. The Read cycle is complete when ML is set to ‘1’, immediately after the MC clock cycle for the least significant bit of indexed control register has completed. AUTO-INCREMENT READ OPERATION The Auto-Increment Read function allows for multiple reg- isters to be read sequentially. The Auto-Increment function is enabled by setting the INC bit of Control Register 21 to ‘1’. The sequence always starts with Register 1, and ends with the register indexed by the REG[6:0] bits in Control Register 21. Figure 9 shows the timing for the Auto-Increment Read operation. The operation begins by writing Control Register 21, setting INC to ‘1’ and setting REG[6:0] to the last register to be read in the sequence. The actual Read opera- tion starts on the next High to Low transition of the ML pin. The Read cycle starts by setting the R/W bit of the control word to ‘1’, and setting all of the IDX[6:0] bits to ‘0’. All subsequent bits input on the MDI are ignored while ML is set to ‘0’. For the first 8 clocks of the Read cycle, MDO is set to a high impedance state. This is followed by a sequence of 8-bit words, each corresponding the data contained in Control Registers 1 through N, where N is defined by the REG[6:0] bits in Control Register 21. The Read cycle is complete when ML is set to ‘1’, immediately after the MC clock cycle for the least significant bit of Control Register N has completed. CONTROL INTERFACE TIMING REQUIREMENTS Figure 10 shows a detailed timing diagram for the serial control interface. Pay special attention to the setup and hold times, as well as tMLS and tMLH, which define minimum delays between edges of the ML and MC clocks. These timing parameters are critical for proper control port operation. |
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