PCM1737ESLASH2K.B datasheet(9/32 Pages) TI2

9 / 32 page

PCM1737

FIGURE 2. Power-On Reset Timing.

FIGURE 3. External Reset Timing.

The external reset is especially useful in applications

where there is a delay between PCM1737 power up and

system clock activation. In this case, the RSTB pin should

be held at a logic ‘0’ level until the system clock has been

activated. The RSTB pin may then be set to a logic ‘1”

state to start the initialization sequence.

AUDIO SERIAL INTERFACE

The audio serial interface for the PCM1737 is comprised of

a 3-wire synchronous serial port. It includes LRCK (pin 1),

BCLK (pin 3), and DATA (pin 2). BCLK is the serial

audio bit clock, and it is used to clock the serial data

present on DATA into the audio interface’s serial shift

rising edge of BCLK. LRCK is the serial audio left/right

word clock. It is used to latch serial data into the serial

audio interface’s internal registers.

Both LRCK and BCLK must be synchronous to the system

clock. Ideally, it is recommended that LRCK and BCLK be

derived from the system clock input or output, SCLK or

CLKO. The left/right clock, LRCK, is operated at the

sampling frequency, fS. The bit clock, BCLK, may be

operated at 48 or 64 times the sampling frequency.

Audio Data Formats and Timing

The PCM1737 supports industry-standard audio data formats,

including standard, I2S, and left-justified. The data formats

are shown in Figure 4. Data formats are selected using the

format bits, FMT[2:0], in Control Register 20. The default

data format is 24-bit standard. All formats require Binary

Two’s Complement, MSB-first audio data. Figure 5 shows a

detailed timing diagram for the serial audio interface.

SERIAL CONTROL INTERFACE

The serial control interface is a 4-wire serial port which

operates asynchronously to the serial audio interface. The

serial control interface is utilized to program and read the on-

chip mode registers. The control interface includes MDO (pin

25), MDI (pin 26), MC (pin 27), and ML (pin 28). MDO is the

serial data output, used to read back the values of the mode

registers. MDI is the serial data input, used to program the

mode registers. MC is the serial bit clock, used to shift data in

and out of the control port. ML is the control port latch clock.

1024 system clocks

Reset

Reset Removal

CC = VDD

Internal Reset

2.4V

2.0V

1.6V

System Clock

(SCLK)

1024 system clocks

Reset

Reset Removal

System Clock

(SCLK)

Internal Reset

RSTB

RST

(1)

NOTE: (1) t

RST = 20ns min.

PCM1737E/2K.B Datasheet(PDF) 9 Page - Texas Instruments

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