TDA8026ETSLASHC3 datasheet(26/61 Pages) NXP

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TDA8026_1

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Product data sheet

Rev. 1.1 — 30 June 2016

26 of 61

NXP Semiconductors

TDA8026

Multiple smart card slot interface IC

8.5.4.3

Bank 1 Register0 card slot 3 (address 03h), card slot 4 (address 04h) and card slot 5

(address 05h) write mode bit descriptions

[1]

This bit cannot be written when START bit is logic 1.

[2]

It is a mandatory condition for card slots 2 to 5 that only one card slot I/O line is enabled at a time. When

switching from one slot to another, the enabled I/O must be disabled before the I/O line for the required card

slot is enabled.

Remark: If both pins I/OUC1 and I/OUC2 are connected at the same time, this mandatory condition also

applies to card slot 1.

[3]

In synchronous mode, this bit cannot be written when START bit is logic 1.

Table 23.

Bank 1 Register0 card slot 3 (address 03h), card slot 4 (address 04h) and card

slot 5 (address 05h) write mode bit descriptions

Bit

Symbol

Value

Description

VCC1V8[1]

used together with the 5V/3VN bit

set to logic 1: VCC(n) = 1.8 V; ignores the 5V/3VN bit logic state

if set to logic 0 VCC(n) is set using the 5V/3VN bit

I/OEN[2]

set to logic 1: pins I/OUCn are switched to pins I/O(n)

set to logic 0: pins I/OUCn and I/O(n) are high-impedance with

internal pull-up resistor

5 to 4

REG[1:0]

see Table 24 “Bank 1 CSb[7:0] Register1 (address 42h) card

slots 3 and 5 bit allocation” on page 27 for detailed information

PWDN[3]

set to logic 1: to apply the CLKPD[1:0] bit clock settings to pin

CLK(n) for the selected card slot

set to logic 0: to apply the CLKDIV[1:0] bits clock options to pin

CLK(n) for the selected card slot

5V/3VN[1]

used together with VCC1V8 bit

set to logic 1: and the VCC1V8 bit is logic 0: VCC(n) = 5 V

set to logic 0: and the VCC1V8 bit is logic 0: VCC(n) = 3 V

WARM

set to logic 1: a warm reset procedure is started

set to logic 0: by the hardware: a START bit is detected or the

MUTE bit is set to logic 1

START

set to logic 1: when the SUPL and PROT bits are logic 0 and the

PRES bit is logic 1, the activation sequence and cold reset

procedure are started

set to logic 0: deactivation sequence starts

TDA8026ET/C3 Datasheet(PDF) 26 Page - NXP Semiconductors

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