SN74AHCT74-EP

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP

WITH CLEAR AND PRESET

SCLS495– JUNE 2003

2

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

FUNCTION TABLE

INPUTS

OUTPUTS

PRE

CLR

CLK

D

Q

Q

L

H

X

X

H

L

H

LX

XL

H

L

LX

X

H†

H†

H

H

↑

HH

L

H

H

↑

LL

H

H

H

L

X

Q0

Q0

† This configuration is unstable; that is, it does not

persist when PRE or CLR returns to its inactive

(high) level.

logic symbol‡

S

4

3

1CLK

1D

2

1D

R

1

1Q

5

6

C1

10

11

2CLK

12

2D

13

2Q

9

8

1PRE

2PRE

1CLR

2CLR

1Q

2Q

‡ This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

logic diagram, each flip-flop (positive logic)

TG

C

C

TG

C

TG

C

C

C

C

TG

C

C

PRE

CLK

D

CLR

Q

Q

C