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SN74LVC2G241YZP Datasheet(PDF) 4 Page - Texas Instruments

Part # SN74LVC2G241YZP
Description  SN74LVC2G241 Dual Buffer and Driver With 3-State Outputs
PDF  25 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

SN74LVC2G241YZP Datasheet(HTML) 4 Page - Texas Instruments

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SN74LVC2G241
SCES210P – APRIL 1999 – REVISED JANUARY 2019
www.ti.com
Product Folder Links: SN74LVC2G241
Submit Documentation Feedback
Copyright © 1999–2019, Texas Instruments Incorporated
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3)
The value of VCC is provided in the Recommended Operating Conditions table.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
UNIT
VCC
Supply voltage
–0.5
6.5
V
VI
Input voltage(2)
–0.5
6.5
V
VO
Voltage applied to any output in the high-impedance or power-off state(2)
–0.5
6.5
V
VO
Voltage applied to any output in the high or low state(2)(3)
–0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
Continuous current through VCC or GND
±100
mA
TJ
Maximum junction temperature
150
°C
Tstg
Storage temperature
–65
150
°C
(1)
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2)
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.2 ESD Ratings
VALUE
UNIT
V(ESD)
Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
±2000
V
Charged-device model (CDM), per JEDEC specification JESD22-C101, all
pins(2)
±1000
(1)
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report
Implications of Slow or Floating CMOS Inputs, SCBA004.
6.3 Recommended Operating Conditions
(1)
MIN
MAX
UNIT
VCC
Supply voltage
Operating
1.65
5.5
V
Data retention only
1.5
VIH
High-level input voltage
VCC = 1.65 V to 1.95 V
0.65 × VCC
V
VCC = 2.3 V to 2.7 V
1.7
VCC = 3 V to 3.6 V
2
VCC = 4.5 V to 5.5 V
0.7 × VCC
VIL
Low-level input voltage
VCC = 1.65 V to 1.95 V
0.35 × VCC
V
VCC = 2.3 V to 2.7 V
0.7
VCC = 3 V to 3.6 V
0.8
VCC = 4.5 V to 5.5 V
0.3 × VCC
VI
Input voltage
0
5.5
V
VO
Output voltage
High or low state
0
VCC
V
3-state
0
5.5
IOH
High-level output current
VCC = 1.65 V
–4
mA
VCC = 2.3 V
–8
VCC = 3 V
–16
–24
VCC = 4.5 V
–32



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