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STM32F205RFT6 Datasheet(PDF) 97 Page - STMicroelectronics |
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STM32F205RFT6 Datasheet(HTML) 97 Page - STMicroelectronics |
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97 / 184 page  DocID15818 Rev 15 97/184 STM32F20xxx Electrical characteristics 183 Jitter(3) Master I2S clock jitter Cycle to cycle at 12.288 MHz on 48KHz period, N=432, R=5 RMS - 90 - ps peak to peak - ±280 - Average frequency of 12.288 MHz N=432, R=5 on 1000 samples -90 - ps WS I2S clock jitter Cycle to cycle at 48 KHz on 1000 samples -400 - ps IDD(PLLI2S)(4) PLLI2S power consumption on VDD VCO freq = 192 MHz VCO freq = 432 MHz 0.15 0.45 - 0.40 0.75 mA IDDA(PLLI2S)(4) PLLI2S power consumption on VDDA VCO freq = 192 MHz VCO freq = 432 MHz 0.30 0.55 - 0.40 0.85 mA 1. Take care of using the appropriate division factor M to have the specified PLL input clock values. 2. Guaranteed by design, not tested in production. 3. Value given with main PLL running. 4. Guaranteed by characterization results, not tested in production. Table 35. PLLI2S (audio PLL) characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit |
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