CTRL1

G1

OFF

EN

G2

t

SU0

t

H0

t

SW

ON

OFF

ON

OFF

OFF

ON

t

SW

OFF

ON

OFF

ON

OFF

OFF

ON

t

WL0

t

WH0

t

SW

t

D

ON

t

SW

t

D

t

D

t

WL1

t

WH1

TLC5960

SBVS147 – SEPTEMBER 2010

www.ti.com

FUNCTIONAL DESCRIPTION

CONTROLLING THE EXTERNAL-FET GATE DRIVERS

The eight-channel TLC5960 is equipped with eight external-FET gate drivers (one per channel) to drive FETs in

series with the LED strings. In normal mode, a CTRL input enables/disables the corresponding two-channel

drivers. That is, CTRL1 turns on the channel 1 (ch1) and ch2 gate drive outputs (G1 and G2) sequentially. A total

of four parallel inputs (CTRL1 to CTRL4) are used to provide eight channels of PWM control. EN high enables

this CTRLn PWM interface, and EN low shuts down all channels simultaneously. The control interface logic truth

table is shown in Table 1.

Table 1. Output Channel Control Truth Table (Normal Mode)

EN

CTRL1

CTRL2

CTRL3

CTRL4

OUTPUT STATUS

Low

X

X

X

X

All channels disabled

Low

Low

Low

Low

All channels disabled

High

Low

Low

Low

Ch1 (G1)/Ch2 (G2) enabled

Low

High

Low

Low

Ch3 (G3)/Ch4 (G4) enabled

High

Low

Low

High

Low

Ch5 (G5)/Ch6 (G6) enabled

Low

Low

Low

High

Ch7 (G7)/Ch8 (G8) enabled

High

High

High

High

All channels enabled

Figure 14 shows the on and off timing of the control input CTRL1 and the related gate driver outputs of ch1 and

ch2. The TLC5960 integrates an internal phase shift function between the channels; therefore, the G1 and G2

outputs on-off timing have an internal unit delay time (tD). Refer to the Built-In Phase Shift and PWM Input

Minimum On-Time Requirement section for more details. The EN signal polarity change, on the other hand,

immediately applies to all channel outputs.

Figure 14. Gate Driver On and Off Timing Sequence

12

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