SN74LVC573

OCTAL TRANSPARENT D-TYPE LATCH

WITH 3-STATE OUTPUTS

SCAS300A – JANUARY 1993 – REVISED NOVEMBER 1994

Copyright

1

POST OFFICE BOX 655303

CMOS ) Submicron Process

Small-Outline (DW), Shrink Small-Outline

(DB), and Thin Shrink Small-Outline (PW)

Packages

description

This octal transparent D-type latch is designed for

The SN74LVC573 features 3-state outputs designed specifically for driving highly capacitive or relatively

low-impedance loads. It is particularly suitable for implementing buffer registers, input/output (I/O) ports,

bidirectional bus drivers, and working registers.

While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the

Q outputs are latched at the logic levels at the D inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high

or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive

the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus

lines without the need for interface or pullup components.

OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered

while the outputs are in the high-impedance state.

The SN74LVC573 is characterized for operation from – 40

°C to 85°C.

FUNCTION TABLE

(each latch)

INPUTS

OUTPUT

OE

LE

D

Q

L

H

H

H

L

HL

L

L

LX

Q0

H

X

X

Z

DB, DW, OR PW PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

OE

1D

2D

3D

4D

5D

6D

7D

8D

GND

1Q

2Q

3Q

4Q

5Q

6Q

7Q

8Q

LE

EPIC is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.