| Electronic Components Datasheet Search |
|
TPL5000 Datasheet(PDF) 3 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
TPL5000 Datasheet(HTML) 3 Page - Texas Instruments |
|
3 / 22 page ![]() D0 D1 TPL5000 D2 VDD PGOOD RSTn WAKE TCAL GND DONE TPL5000 www.ti.com SNAS628B – JULY 2013 – REVISED DECEMBER 2014 6 Pin Configuration and Functions 10-Lead VSSOP Top View Pin Functions PIN DESCRIPTION APPLICATION INFORMATION NAME NO. D0 1 Logic Input to set period delay (tDP) Connect to either GND (low logic value) or VDD (high logic value) D1 2 Logic Input to set period delay (tDP) Connect to either GND (low logic value) or VDD (high logic value) D2 3 Logic Input to set period delay (tDP) Connect to either GND (low logic value) or VDD (high logic value) VDD 4 Supply voltage GND 5 Ground DONE 6 Logic Input for watchdog functionality TCAL 7 Short duration pulse output for estimation of TPL5000 timer delay. WAKE 8 Timer output signal generated every tDP period. RSTn 9 Reset Output (open drain output) PGOOD 10 Digital power good input Copyright © 2013–2014, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: TPL5000 |
|
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |