TPL5000

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SNAS628B – JULY 2013 – REVISED DECEMBER 2014

Feature Description (continued)

8.3.2 Configuration and Interface

The time interval between 2 adjacent WAKE pulses (or 2 adjacent RSTn pulses or RSTn and WAKE pulses) is

selectable through 3 digital input pins (D0, D1, D2). These pins can be strapped to either VDD (1) or GND (0).

Eight possible time delays can be selected, as shown in Table 1.

Table 1. Timer Delay Period

D2

D1

D0

Time (s)

Factor N

0

0

0

1

26

0

0

1

2

27

0

1

0

4

28

0

1

1

8

29

1

0

0

10

10*26

1

0

1

16

210

1

1

0

32

211

1

1

1

64

212

8.4 Device Functional Modes

The TPL5000 mode of operations are selected through the PGOOD pin. There are two factors to consider when

the PGOOD pin is at a high-logic level or low-logic level. When the PGOOD pin is at a high-logic level, the

TPL5000 works as a timer and conversely at a low-logic level the TLP5000 does not work as a timer. For best

use of TPL5000 waiting for high-logic is necessary.

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