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ADS8370

+IN

−IN

THS4031

20 W

20 W

1.5 nF

50 W

Input

Signal

(0 V to 4 V)

ADS8370

+IN

−IN

THS4031

20 W

20 W

1.5 nF

600 W

1 V DC

600 W

Input

Signal

(−2V to 2 V)

DIGITAL INTERFACE

TIMING AND CONTROL

ADS8370

SLAS450 – JUNE 2005

PRINCIPLES OF OPERATION (continued)

signals. Essentially, the current into the ADS8370 charges the internal capacitor array during the sampling

(acquisition) time. After this capacitance has been fully charged, there is no further input current. The source of

the analog input voltage must be able to charge the device sampling capacitance (40 pF each from +IN/–IN to

AGND) to an 16-bit settling level within the sampling (acquisition) time of the device. When the converter goes

into hold mode, the input resistance is greater than 1 G

Ω.

Care must be taken regarding the absolute analog input voltage. To maintain the linearity of the converter, the

+IN, –IN inputs and the span [+IN – (–IN)] should be within the limits specified. Outside of these ranges, the

converter's linearity may not meet specifications.

Care should be taken to ensure that the output impedance of the sources driving +IN and –IN inputs are

matched. If this is not observed, the two inputs can have different settling times. This can result in offset error,

gain error, and linearity error which vary with temperature and input voltage.

A typical input circuit using TI's THS4031 is shown in Figure 52. In the figure, input from a bipolar source is

converted to a unipolar signal for the ADS8370. In the case where the source signal is in range for the

ADS8370, the circuit in Figure 51 may be used. Most of the specified performance figure were measured using

the circuit in Figure 51.

Figure 51. Unipolar Input Drive Configuration

Figure 52. Bipolar Input Drive Configuration

Conversion and sampling are controlled by the CONVST and CS pins. See the timing diagrams for detailed

information on timing signals and their requirements. The ADS8370 uses an internally generated clock to control

the conversion rate and in turn the throughput of the converter. SCLK is used for reading converted data only. A

clean and low jitter conversion start command is important for the performance of the converter. There is a

minimal quiet zone requirement around the conversion start command as mentioned in the timing requirements

table.

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