Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

TSB41AB3IPFPEP Datasheet(PDF) 27 Page - Texas Instruments

Part # TSB41AB3IPFPEP
Description  IEEE 1394a-2000 THREE-PORT CABLE TRANSCEIVER/ARBITER
PDF  56 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

TSB41AB3IPFPEP Datasheet(HTML) 27 Page - Texas Instruments

Back Button TSB41AB3IPFPEP Datasheet HTML 23Page - Texas Instruments TSB41AB3IPFPEP Datasheet HTML 24Page - Texas Instruments TSB41AB3IPFPEP Datasheet HTML 25Page - Texas Instruments TSB41AB3IPFPEP Datasheet HTML 26Page - Texas Instruments TSB41AB3IPFPEP Datasheet HTML 27Page - Texas Instruments TSB41AB3IPFPEP Datasheet HTML 28Page - Texas Instruments TSB41AB3IPFPEP Datasheet HTML 29Page - Texas Instruments TSB41AB3IPFPEP Datasheet HTML 30Page - Texas Instruments TSB41AB3IPFPEP Datasheet HTML 31Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 27 / 56 page
background image
TSB41AB3EP
IEEE 1394a2000 THREEPORT CABLE TRANSCEIVER/ARBITER
SGLS122C − JULY 2002 − REVISED JUNE 2008
27
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
APPLICATION INFORMATION
using the TSB41AB3 with a non-1394a-2000 link layer (continued)
The 1394a-2000 Supplement includes enhancements to the Annex J interface that must be comprehended
when using the TSB41AB3 with a non-1394a-2000 LLC device.
D A new LLC service request was added which allows the LLC to temporarily enable and disable
asynchronous arbitration accelerations. If the LLC does not implement this new service request, the
arbitration enhancements is not enabled (see the EAA bit in PHY register 5).
D The capability to perform multispeed concatenation (the concatenation of packets of differing speeds) was
added in order to improve bus efficiency (primarily during isochronous transmission). If the LLC does not
support multispeed concatenation, multispeed concatenation is not enabled in the PHY (see the EMC bit
in PHY register 5).
D In order to accommodate the higher transmission speeds expected in future revisions of the standard,
1394a-2000 extended the speed code in bus requests from 2 bits to 3 bits, increasing the length of the bus
request from 7 bits to 8 bits. The new speed codes were carefully selected so that new 1394a-2000 PHY
and LLC devices would be compatible, for speeds from S100 to S400, with legacy PHY and LLC devices
that use the 2-bit speed codes. The TSB41AB3 correctly interprets both 7-bit bus requests (with 2-bit speed
code) and 8-bit bus requests (with 3-bit speed codes). Moreover, if a 7-bit bus request is immediately
followed by another request (e.g., a register read or write request), the TSB41AB3 correctly interprets both
requests. Although the TSB41AB3 correctly interprets 8-bit bus requests, a request with a speed code
exceeding S400 results in the TSB41AB3 transmitting a null packet (data-prefix followed by data-end, with
no data in the packet).
More explanation is included in the TI application note IEEE 1394a-2000 Features Supported by TI TSB41LV0X
Physical Layer Devices, TI literature number SLLA019.
using the TSB41AB3 with a lower-speed link layer
Although the TSB41AB3 is an S400-capable PHY, it may be used with lower speed LLCs, such as the S200
capable TSB12LV31. In such a case, the LLC has fewer data terminals than the PHY, and some Dn terminals
on the TSB41AB3 are not used. Unused Dn terminals are pulled to ground through 10-k
Ω resistors.
The TSB41AB3 transfers all received packet data to the LLC, even if the speed of the packet exceeds the
capability of the LLC to accept it. Some lower speed LLC designs do not properly ignore packet data in such
cases. On the rare occasions that the first 16 bits of partial data accepted by such a LLC match a node’s bus
and node ID, spurious header CRC or tcode errors may result.
During bus initialization following a bus-reset, each PHY transmits a self-ID packet that indicates, among other
information, the speed capability of the PHY. The bus manager (if one exists) builds a speed map from the
collected self-ID packets. This speed map gives the highest possible speed that can be used on the
node-to-node communication path between every pair of nodes in the network.
In the case of a node consisting of a higher-speed PHY and a lower-speed LLC, the speed capability of the node
(PHY and LLC in combination) is that of the lower-speed LLC. A sophisticated bus manager may be able to
determine the LLC speed capability by reading the configuration ROM Bus_Info_Block or by sending
asynchronous request packets at different speeds to the node and checking for an acknowledge; the speed map
may then be adjusted accordingly. The speed-map should reflect that communication to such a node must be
done at the lower speed of the LLC, instead of the higher speed of the PHY. However, speed map entries for
paths that merely pass through the node’s PHY, but do not terminate at that node, are not restricted by the lower
speed of the LLC.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com