TSB41AB3MPFPEP datasheet(45/56 Pages) TI2

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TSB41AB3EP

IEEE 1394a2000 THREEPORT CABLE TRANSCEIVER/ARBITER

SGLS122C − JULY 2002 − REVISED JUNE 2008

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

interface reset and disable (continued)

The sequence of events for resetting the PHY-LLC interface when it is in the nondifferentiated mode of operation

(ISO terminal is high) is as follows:1

Normal operation. Interface is operating normally, with LPS asserted, SYSCLK active, status and

packet data reception and transmission via the CTL and D lines, and request activity via the LREQ line.

In Figure 23, the LPS signal is shown as a non-pulsed level signal. However, it is permissible to use

a pulsed signal for LPS in a direct connection between the PHY and LLC; a pulsed signal is required

when using an isolation barrier (whether of the TI bus holder type or Annex J type).

LPS deasserted. The LLC deasserts the LPS signal and, within 1

µs, terminates any request or interface

bus activity, places its CTL and D outputs into a high-impedance state, and drives its LREQ output low.

Interface reset. After TLPS_RESET time, the PHY determines that LPS is inactive, terminates any

interface bus activity, and drives its CTL and D outputs low. The PHY-LLC interface is now in the reset

state.

Interface restored. After the minimum TRESTORE time, the LLC may again assert LPS active. When LPS

is asserted, the interface initializes as described below.

If the LLC continues to keep the LPS signal deasserted, it requests that the interface be disabled. The PHY

disables the interface when it observes that LPS has been deasserted for TLPS_DISABLE. When the interface

is disabled, the PHY sets its CTL and D outputs as stated above for interface reset, but also stops SYSCLK

activity. The interface is also placed into the disabled condition upon a hardware reset of the PHY. The timing

for interface disable is shown in Figure 24 and Figure 25.

When the interface is disabled, the PHY enters a low-power state if none of its ports is active.

SYSCLK

ISO

(low)

(a)

(c)

(b)

CTL0, CTL1

D0 − D7

LREQ

LPS

(d)

TLPS_RESET

TLPS_DISABLE

TLPSL TLPSH

Figure 25. Interface Disable, ISO Low

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