11

ADS7835

®

500kHz conversion rate.

HIGH.

SHORT-CYCLE TIMING

The conversion currently in progress can be “short-cycled”

with the technique shown in Figure 6. This term means that

the conversion will terminate immediately, before all 12 bits

have been decided. This can be a very useful feature when

a resolution of 12 bits is not needed. An example would be

when the converter is being used to monitor an input voltage

until some condition is met. At that time, the full resolution

of the converter would then be used. Short-cycling the

conversion can result in a faster conversion rate or lower

power dissipation.

There are several very important items shown in Figure 6.

The conversion currently in progress is terminated when

CONV is taken HIGH during the conversion and then taken

LOW prior to tCKCH before the start of the 13th clock cycle.

Note that if CONV goes LOW during the 13th clock cycle,

the LSB-first mode will be entered (Figure 5). Additionally,

when CONV goes LOW, the DATA output immediately

transitions to high impedance. If the output bit that is present

during that clock period is needed, CONV must not go LOW

until the bit has been properly latched into the receiving

POWER WITH

POWER WITH

fSAMPLE

CLK = 16 • fSAMPLE

CLK = 8MHz

500kHz

17.5mW

17.5mW

250kHz

16.5mW

13.5mW

100kHz

15.5mW

10.5mW

TABLE II. Power Consumption versus CLK Input.

Table II offers a look at the two different modes of operation

and the difference in power consumption.

LSB-FIRST DATA TIMING

Figure 5 shows a method to transmit the digital result in a

LSB format. This mode is entered when CONV is pulled

HIGH during the conversion (before the end of the 12th

clock) and then pulled LOW during the 13th clock (when

D0, the LSB, is being transmitted). The next 11 clocks then

repeat the serial data, but in an LSB-first format. The

converter enters the power-down mode during the 13th

clock and resumes normal operation when CONV goes

FIGURE 6. Short-Cycle Timing.

D11

(MSB)

DATA

CONVERSION IN PROGRESS

IDLE

IDLE

CLK

CONV

POWER MODE

FULL POWER

LOW POWER

D10

D8

D9

D7

12

3

5

46

7

D6

INTERNAL

CONVERSION

STATE

t

CVDD

t

CVL

t

CVH

HOLD

SAMPLE

SAMPLE/HOLD

MODE

NOTE: (1) The conversion currently in progress can be stopped by pulling CONV LOW during the conversion. This must occur at

least t

CKCS prior to the start of the 13th clock cycle. The DATA output pin will tri-state and the device will enter the power-down

mode when CONV is pulled LOW.

(1)

t

CVPD