12

ADS7835

®

logic.

DATA FORMAT

The ADS7835 output data is in Binary Two’s Complement

format as shown in Table III. This table shows the ideal

output code for the given input voltage and does not include

Figure 7 shows a timing diagram that might be used with a

typical digital signal processor such as a TI DSP. For the

Buffered Serial Port (BSP) on the TMS320C54X family,

CONV would tied to BFSX, CLK would be tied to BCLKX,

and DATA would be tied to BDR.

SPI/QSPI INTERFACING

Figure 8 shows the timing diagram for a typical Serial

Peripheral Interface (SPI) or Queued Serial Peripheral Inter-

face (QSPI). Such interfaces are found on a number of

microcontrollers from various manufacturers. CONV would

be tied to a general purpose I/O pin (SPI) or to a PCX pin

(QSPI), CLK would be tied to the serial clock, and DATA

would be tied to the serial input data pin such as MISO

(Master In Slave Out).

Note the time tDRP shown in Figure 8. This represents the

maximum amount of time between CONV going LOW and

the start of the conversion clock. Since CONV going LOW

places the S/H in the hold mode and because the hold

capacitor loses charge over time, there is a requirement that

time tDRP be met as well as the maximum clock period

D11

(MSB)

DATA

CLK

CONV

D10

D1

D0

(LSB)

23

1

4

13

14

15

16

1

2

3

D11

(MSB)

t

ACQ

t

DRP

FIGURE 8. Typical SPI/QSPI Interface Timing.

FIGURE 7. Typical DSP Interface Timing.

D11

(MSB)

DATA

CLK

CONV

D10

D1

D0

(LSB)

12

15

16

3

12

13

14

15

16

1

2

3

4

D11

(MSB)

D10

D9

DESCRIPTION

ANALOG INPUT

DIGITAL OUTPUT

Full-Scale Input

BINARY TWO’S

Range

–VREF to +VREF(1)

COMPLEMENT

Least Significant Bit

BINARY

HEX

(LSB)(2)

(–VREF to +VREF)/4096

CODE

CODE

+Full Scale

2.49878V

0111 1111 1111

7FF

Mid-Scale

0V

0000 0000 0000

000

Mid-Scale –1LSB

–0.00122V

1111 1111 1111

FFF

–Full Scale

–2.49878V

1000 0000 0000

800

NOTES: (1) –2.5V to +2.5V when the internal reference is used. (2) 1.22mV

with a 2.5V reference.

TABLE III. Ideal Input Voltages and Output Codes.

the effects of offset, gain, or noise.

DSP INTERFACING