7.4 Device Functional Modes

Table 7-1 is the function table for CDC3RL02.

Table 7-1. Function Table

INPUTS

OUTPUTS

CLK_REQ1(1)

CLK_REQ2(1)

MCLK_IN

CLK_OUT1

CLK_OUT2

L

L

X

L

L

L

H

CLK

L

CLK

H

L

CLK

CLK

L

H

H

CLK

CLK

CLK

(1)

If a CLK_OUT is always enabled, tying the CLK_REQ pin to an external 1.8V source (not VLDO) is acceptable.

8 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI’s customers are responsible for

determining suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

8.1 Application Information

8.1.1 Input Clock Squarer

Figure 8-1 shows the input stage of the CDC3RL02. The input signal at MCLK_IN can be a square wave or

sine wave. CMCLK is an internal AC coupling capacitor that allows a direct connection from the TCXO to the

CDC3RL02 without an external capacitor.

MCLK _IN

C

MCLK

Figure 8-1. Input Stage With Internal AC Coupling Capacitor

Any external component added in the series path of the clock signal potentially adds phase noise and jitter. The

error source associated with the internal decoupling capacitor is included in the specification of the CDC3RL02.

The recommended clock frequency band of the CDC3RL02 is 10MHz to 80MHz for specified functionality. All

performance metrics are specified at 26MHz. The lowest acceptable sinusoidal signal amplitude is 0.8VPP for

specified performance. Amplitudes as low as 0.3VPP are acceptable but with reduced phase-noise and jitter

performance.

8.1.2 Output Stage

Each output drives 1.8V LVCMOS levels. Adaptive output buffers limit the rise/fall time of the output to within

1ns to 5ns with load capacitance between 10pF and 50pF. Fast slew rates introduce EMI into the system. Each

output buffer limits EMI by keeping the rise/fall time above 1ns. Slow rise/fall times can induce additive phase

noise and duty cycle errors in the load device. The output buffer limits these errors by keeping the rise/fall time

below 5ns. In addition, the output stage dynamically alters impedance based on the instantaneous voltage level

of the output. This dynamic change limits reflections keeping the output signal monotonic during transitions.

Each output is active low when not requested to avoid false clocking of the load device.

8.1.3 LDO

A low noise 1.8V LDO is integrated to provide the I/O supply for the output buffers. The LDO output is externally

available to power a clock source such as a TCXO. A clean supply is provided to the clock buffers and the clock

CDC3RL02

SCHS371H – NOVEMBER 2009 – REVISED OCTOBER 2024

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