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TIMING CHARACTERISTICS: VDD = 5 V

(1) (2)

TIMING CHARACTERISTICS: VDD = 3 V

(1) (2)

DAC8830-EP

DAC8831-EP

SGLS334C – AUGUST 2006 – REVISED APRIL 2007

At –55

°C to 125°C (unless otherwise noted)

PARAMETER

MIN

MAX

UNIT

tsck

SCLK period

20

ns

twsck

SCLK high or low time

10

ns

tDelay

Delay from SCLK high to CS low

18

ns

tLead

CS enable lead time

12

ns

tLag

CS enable lag time

15

ns

tDSCLK

Delay from CS high to SCLK high

15

ns

ttd

CS high between active period

30

ns

tsu

Data setup time (input)

10

ns

tho

Data hold time (input)

0

ns

tWLDAC

LDAC width

30

ns

tDLDAC

Delay from CS high to LDAC low

30

ns

VDD high to CS low (power-up delay)

10

μs

(1)

Specified by design. Not production tested.

(2)

Sample tested during the initial release and after any redesign or process changes that may affect this parameter.

At –55

°C to 125°C (unless otherwise noted)

PARAMETER

MIN

MAX

UNIT

tsck

SCLK period

20

ns

twsck

SCLK high or low time

10

ns

tDelay

Delay from SCLK high to CS low

18

ns

tLead

CS enable lead time

15

ns

tLag

CS enable lag time

15

ns

tDSCLK

Delay from CS high to SCLK high

15

ns

ttd

CS high between active period

30

ns

tsu

Data setup time (input)

10

ns

tho

Data hold time (input)

0

ns

tWLDAC

LDAC width

30

ns

tDLDAC

Delay from CS high to LDAC low

30

ns

VDD high to CS low (power-up delay)

10

μs

(1)

Specified by design. Not production tested.

(2)

Sample tested during the initial release and after any redesign or process changes that may affect this parameter.

9

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