VVF-CAP =

2

VAC-RMS

2

+

+

D3

C7

C9

C10

D4

D8

VBUCK

V+

+

-

+

-

2

VBUCK

2

VBUCK

+

+

D3

C7

C8

C9

C10

D4

D5

D6

D7

D8

R7

R8

D9

R6

VBUCK

V+

+

+

D3

C7

C9

C10

D4

D8

D9

R7

R6

R8

VBUCK

V+

LM3444

SNVS682D – NOVEMBER 2010 – REVISED DECEMBER 2015

www.ti.com

Feature Description (continued)

Figure 9. Two and Three Stage Valley Fill Circuit

The valley-fill circuit allows the buck regulator to draw power throughout a larger portion of the AC line. This

allows the capacitance needed at VBUCK to be lower than if there were no valley-fill circuit, and adds passive

power factor correction (PFC) to the application.

7.3.3 Valley-Fill Operation

When the input line is high, power is derived directly through D3. The term input line is high is explained as

follows. The valley-fill circuit charges capacitors C7 and C9 in series (Figure 10) when the input line is high.

Figure 10. Two Stage Valley-Fill Circuit When AC Line is High

The peak voltage of a two-stage valley-fill capacitor is given by Equation 1.

(1)

As the AC line decreases from its peak value every cycle, there is a point where the voltage magnitude of the AC

line is equal to the voltage that each capacitor is charged. At this point, diode D3 becomes reversed biased, and

the capacitors are placed in parallel to each other (Figure 11), and VBUCK equals the capacitor voltage.

10

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