LM3550SPXSLASHNOPB datasheet(36/43 Pages) TI2

36 / 43 page

4.2 mm

3 mm

Current Source

Super-Capacitor

Charger

LM3550

SNVS569C – MAY 2009 – REVISED OCTOBER 2016

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10 Layout

10.1 Layout Guidelines

The UQFN is a leadless package with very good thermal properties. This package has an exposed DAP (die

attach pad) at the underside center of the package measuring 1.86 mm × 2.2 mm. The main advantage of this

exposed DAP is to offer low thermal resistance when soldered to the thermal ground pad on the PCB. For good

PCB layout TI recommends a 1:1 ratio between the package and the PCB thermal land. To further enhance

thermal conductivity, the PCB thermal ground pad may include vias to a 2nd layer ground plane. For more

detailed instructions on mounting UQFN packages, refer to AN-1187 Leadless Leadframe Package (LLP).

The proceeding steps must be followed to ensure stable operation and proper current source regulation.

1. Bypass VIN with at least a 4.7-µF ceramic capacitor. Connect the positive terminal of this capacitor as close

as possible to VIN.

2. Connect COUT as close as possible to the VOUT pin with at least a 2.2-µF capacitor.

3. Connect the return terminals of the input capacitor and the output capacitor as close as possible to the

exposed DAP and GND pins through low impedance traces.

4. Place the two 1-µF flying capacitors (C1 and C2) as close as possible to the LM3550 C1+, C1

− and C2+,

− pins.

5. To minimize losses during the flash pulse, TI recommends that the flash LEDs, the current source NFET,

and current-setting resistor be placed as close as possible to the super capacitor.

10.2 Layout Example

Figure 72. LM3550 Layout

LM3550SPX/NOPB Datasheet(PDF) 36 Page - Texas Instruments