5

LM3550

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SNVS569C – MAY 2009 – REVISED OCTOBER 2016

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Copyright © 2009–2016, Texas Instruments Incorporated

(1)

All voltages are with respect to the potential at the GND pin.

(2)

Junction-to-ambient thermal resistance (RθJA) is taken from a thermal modeling result, performed under the conditions and guidelines set

forth in the JEDEC standard JESD51-7. The test board is a 4-layer FR-4 board measuring 102 mm × 76 mm × 1.6 mm with a 2 × 1

array of thermal vias. The ground plane on the board is 50 mm x 50 mm. Thickness of copper layers are 36 µm/18 µm/18 µm/36 µm

(1.5oz/1oz/1oz/1.5oz). Ambient temperature in simulation is 22°C, still air. Power dissipation is 1 W.

(3)

Minimum (MIN) and maximum (MAX) limits are specified by design, test, or statistical analysis. Typical (TYP) numbers are not ensured,

but do represent the most likely norm. Unless otherwise specified, conditions for TYP specifications are: VIN = 3.6 V and TA = 25°C.

6.5 Electrical Characteristics

Typical imits are for TJ = 25°C; minimum and maximum limits apply over the full ambient junction temperature range (−30°C ≤

TA ≤ 85°C). Unless otherwise noted, specifications apply to Typical Application with: : VIN = 3.6 V, CIN = 4.7 µF, COUT = 2.2

µF, C1 = C2 = 1 µF.

(1) (2)

PARAMETER

TEST CONDITION

MIN(3)

TYP

MAX(3)

UNIT

ILED–

Current sink accuracy

2.7 V

≤ VIN ≤ 5.5 V

3 V

≤ VIN ≤ 5.5 V

54

60

66

mA

90

100

110

180

200

220

VOVP

Output overvoltage protection

2.7 V

≤ VIN ≤ 5.5 V

Going into OVP

5.3

5.479

V

Hysteresis

0.2

VOUT

Output voltage regulation

2.7 V

≤ VIN ≤ 5.5 V, IOUT = 0 mA

4.275

4.5

4.666

V

4.75

5

5169

5.035

5.3

5.479

VBAL

BAL pin voltage regulation

2.7 V

≤ VIN ≤ 5.5 V

VOUT / 2

IIND

IND pin current regulation

2.7 V

≤ VIN ≤ 5.5 V, VIND = 2 V

3.3

4.8

6.3

mA

ƒSW

Switching frequency

2.7 V

≤ VIN ≤ 5.5 V

0.882

1

1.153

MHz

VFB

FEEDBACK pin regulation

voltage

2.7 V

≤ VIN ≤ 5.5 V, VOUT = 4.6 V

94

100

106

mV

VALD/TEMP

ALD/TEMP pin reference voltage

2.7 V

≤ VIN ≤ 5.5 V

095

1

1.05

V

VEOC

EOC pin output logic load

ILOAD = 3 mA

400

mV

IIN-CL

Input current limit

VOUT = 0 V

534

610

mA

ISD

Shutdown supply current

Device disabled, 2.7 V

≤ VIN ≤ 5.5 V

1.8

4

µA

IQ

Quiescent supply current

2.7 V

≤ VIN ≤ 5.5 V, IOUT = 0 mA

5-V charge mode, non switching

168

240

µA

VSTROBE

STROBE logic thresholds

2.7 V

≤ VIN ≤ 5.5 V

High

1.23

VIN

V

Low

0

0.7

I2C-COMPATIBLE VOLTAGE SPECIFICATIONS (SCL, SDA)

VIL

Input logic low

2.7 V

≤ VIN ≤ 5.5 V

0

0.7

V

VIH

Input logic high

2.7 V

≤ VIN ≤ 5.5 V

1.23

VIN

V

VOL

Output logic low

ILOAD = 3 mA

400

mV

6.6 Timing Requirements

MIN

NOM

MAX

UNIT

t1

SCK (clock period)

294

ns

t2

Data in setup time to SCL high, ƒSCL = 400 kHz

100

ns

t3

Data out stable after SCL low, ƒSCL = 400 kHz

0

ns

t4

SDA low setup time to SCL low (start), fSCL = 400 kHz

100

ns

t5

SDA igh hold time after SCL high (stop), fSCL = 400 kHz

100

ns