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LM5035BSQ/NOPB Datasheet(PDF) 3 Page - Texas Instruments |
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LM5035BSQ/NOPB Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 37 page  CS NC AGND RT COMP OVP SS HO LO PGND VCC SR1 SR2 REF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 EP LM5035B www.ti.com SNVS613C – JULY 2009 – REVISED APRIL 2013 Figure 2. WQFN-24 Package Top View PIN DESCRIPTIONS TSSOP WQFN Name Description Application Information PIN PIN 1 23 RAMP Modulator ramp signal An external RC circuit from VIN sets the ramp slope. This pin is discharged at the conclusion of every cycle by an internal FET. Discharge is initiated by either the internal clock or the Volt • Second clamp comparator. 2 24 UVLO Line Under-Voltage Lockout An external voltage divider from the power source sets the shutdown and standby comparator levels. When UVLO reaches the 0.4V threshold the VCC and REF regulators are enabled. When UVLO reaches the 1.25V threshold, the SS pin is released and the device enters the active mode. Hysteresis is set by an internal current sink that pulls 23 µA from the external resistor divider. 3 2 OVP Line Over-Voltage Protection An external voltage divider from the power source sets the shutdown levels. The threshold is 1.25V. Hysteresis is set by an internal current source that sources 23µA into the external resistor divider. 4 3 COMP Input to the Pulse Width Modulator An external opto-coupler connected to the COMP pin sources current into an internal NPN current mirror. The PWM duty cycle is maximum with zero input current, while 1mA reduces the duty cycle to zero. The current mirror improves the frequency response by reducing the AC voltage across the opto-coupler detector. 5 4 RT Oscillator Frequency Control and Normally biased at 2V. An external resistor connected between RT Sync Clock Input. and AGND sets the internal oscillator frequency. The internal oscillator can be synchronized to an external clock with a frequency higher than the free running frequency set by the RT resistor. 6 5 AGND Analog Ground Connect directly to Power Ground. 7 6 CS Current Sense input for current If CS exceeds 0.25V the output pulse will be terminated, entering limit cycle-by-cycle current limit. An internal switch holds CS low for 50ns after HO or LO switches high to blank leading edge transients. Copyright © 2009–2013, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: LM5035B |
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